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[PULL 27/49] hw/misc/mps2-scc: Support configurable number of OSCCLK val
From: |
Peter Maydell |
Subject: |
[PULL 27/49] hw/misc/mps2-scc: Support configurable number of OSCCLK values |
Date: |
Fri, 5 Mar 2021 17:14:53 +0000 |
Currently the MPS2 SCC device implements a fixed number of OSCCLK
values (3). The variant of this device in the MPS3 AN524 board has 6
OSCCLK values. Switch to using a PROP_ARRAY, which allows board code
to specify how large the OSCCLK array should be as well as its
values.
With a variable-length property array, the SCC no longer specifies
default values for the OSCCLKs, so we must set them explicitly in the
board code. This defaults are actually incorrect for the an521 and
an505; we will correct this bug in a following patch.
This is a migration compatibility break for all the mps boards.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210215115138.20465-3-peter.maydell@linaro.org
---
include/hw/misc/mps2-scc.h | 7 +++----
hw/arm/mps2-tz.c | 5 +++++
hw/arm/mps2.c | 5 +++++
hw/misc/mps2-scc.c | 24 +++++++++++++-----------
4 files changed, 26 insertions(+), 15 deletions(-)
diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h
index f65d8732031..514da49f69e 100644
--- a/include/hw/misc/mps2-scc.h
+++ b/include/hw/misc/mps2-scc.h
@@ -19,8 +19,6 @@
#define TYPE_MPS2_SCC "mps2-scc"
OBJECT_DECLARE_SIMPLE_TYPE(MPS2SCC, MPS2_SCC)
-#define NUM_OSCCLK 3
-
struct MPS2SCC {
/*< private >*/
SysBusDevice parent_obj;
@@ -39,8 +37,9 @@ struct MPS2SCC {
uint32_t dll;
uint32_t aid;
uint32_t id;
- uint32_t oscclk[NUM_OSCCLK];
- uint32_t oscclk_reset[NUM_OSCCLK];
+ uint32_t num_oscclk;
+ uint32_t *oscclk;
+ uint32_t *oscclk_reset;
};
#endif
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index 82ce6262817..7c066c11ed4 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -219,6 +219,11 @@ static MemoryRegion *make_scc(MPS2TZMachineState *mms,
void *opaque,
qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008);
qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
+ /* This will need to be per-FPGA image eventually */
+ qdev_prop_set_uint32(sccdev, "len-oscclk", 3);
+ qdev_prop_set_uint32(sccdev, "oscclk[0]", 50000000);
+ qdev_prop_set_uint32(sccdev, "oscclk[1]", 24576000);
+ qdev_prop_set_uint32(sccdev, "oscclk[2]", 25000000);
sysbus_realize(SYS_BUS_DEVICE(scc), &error_fatal);
return sysbus_mmio_get_region(SYS_BUS_DEVICE(sccdev), 0);
}
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index 39add416db5..81413b7133e 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -373,6 +373,11 @@ static void mps2_common_init(MachineState *machine)
qdev_prop_set_uint32(sccdev, "scc-cfg4", 0x2);
qdev_prop_set_uint32(sccdev, "scc-aid", 0x00200008);
qdev_prop_set_uint32(sccdev, "scc-id", mmc->scc_id);
+ /* All these FPGA images have the same OSCCLK configuration */
+ qdev_prop_set_uint32(sccdev, "len-oscclk", 3);
+ qdev_prop_set_uint32(sccdev, "oscclk[0]", 50000000);
+ qdev_prop_set_uint32(sccdev, "oscclk[1]", 24576000);
+ qdev_prop_set_uint32(sccdev, "oscclk[2]", 25000000);
sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(sccdev), 0, 0x4002f000);
object_initialize_child(OBJECT(mms), "fpgaio",
diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c
index ce1dfe93562..52a4e183b71 100644
--- a/hw/misc/mps2-scc.c
+++ b/hw/misc/mps2-scc.c
@@ -57,7 +57,7 @@ static bool scc_cfg_write(MPS2SCC *s, unsigned function,
{
trace_mps2_scc_cfg_write(function, device, value);
- if (function != 1 || device >= NUM_OSCCLK) {
+ if (function != 1 || device >= s->num_oscclk) {
qemu_log_mask(LOG_GUEST_ERROR,
"MPS2 SCC config write: bad function %d device %d\n",
function, device);
@@ -75,7 +75,7 @@ static bool scc_cfg_write(MPS2SCC *s, unsigned function,
static bool scc_cfg_read(MPS2SCC *s, unsigned function,
unsigned device, uint32_t *value)
{
- if (function != 1 || device >= NUM_OSCCLK) {
+ if (function != 1 || device >= s->num_oscclk) {
qemu_log_mask(LOG_GUEST_ERROR,
"MPS2 SCC config read: bad function %d device %d\n",
function, device);
@@ -227,7 +227,7 @@ static void mps2_scc_reset(DeviceState *dev)
s->cfgctrl = 0x100000;
s->cfgstat = 0;
s->dll = 0xffff0001;
- for (i = 0; i < NUM_OSCCLK; i++) {
+ for (i = 0; i < s->num_oscclk; i++) {
s->oscclk[i] = s->oscclk_reset[i];
}
for (i = 0; i < ARRAY_SIZE(s->led); i++) {
@@ -254,12 +254,14 @@ static void mps2_scc_realize(DeviceState *dev, Error
**errp)
LED_COLOR_GREEN, name);
g_free(name);
}
+
+ s->oscclk = g_new0(uint32_t, s->num_oscclk);
}
static const VMStateDescription mps2_scc_vmstate = {
.name = "mps2-scc",
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.fields = (VMStateField[]) {
VMSTATE_UINT32(cfg0, MPS2SCC),
VMSTATE_UINT32(cfg1, MPS2SCC),
@@ -268,7 +270,8 @@ static const VMStateDescription mps2_scc_vmstate = {
VMSTATE_UINT32(cfgctrl, MPS2SCC),
VMSTATE_UINT32(cfgstat, MPS2SCC),
VMSTATE_UINT32(dll, MPS2SCC),
- VMSTATE_UINT32_ARRAY(oscclk, MPS2SCC, NUM_OSCCLK),
+ VMSTATE_VARRAY_UINT32(oscclk, MPS2SCC, num_oscclk,
+ 0, vmstate_info_uint32, uint32_t),
VMSTATE_END_OF_LIST()
}
};
@@ -280,14 +283,13 @@ static Property mps2_scc_properties[] = {
DEFINE_PROP_UINT32("scc-cfg4", MPS2SCC, cfg4, 0),
DEFINE_PROP_UINT32("scc-aid", MPS2SCC, aid, 0),
DEFINE_PROP_UINT32("scc-id", MPS2SCC, id, 0),
- /* These are the initial settings for the source clocks on the board.
+ /*
+ * These are the initial settings for the source clocks on the board.
* In hardware they can be configured via a config file read by the
* motherboard configuration controller to suit the FPGA image.
- * These default values are used by most of the standard FPGA images.
*/
- DEFINE_PROP_UINT32("oscclk0", MPS2SCC, oscclk_reset[0], 50000000),
- DEFINE_PROP_UINT32("oscclk1", MPS2SCC, oscclk_reset[1], 24576000),
- DEFINE_PROP_UINT32("oscclk2", MPS2SCC, oscclk_reset[2], 25000000),
+ DEFINE_PROP_ARRAY("oscclk", MPS2SCC, num_oscclk, oscclk_reset,
+ qdev_prop_uint32, uint32_t),
DEFINE_PROP_END_OF_LIST(),
};
--
2.20.1
- [PULL 29/49] hw/arm/mps2-tz: Make the OSCCLK settings be configurable per-board, (continued)
- [PULL 29/49] hw/arm/mps2-tz: Make the OSCCLK settings be configurable per-board, Peter Maydell, 2021/03/05
- [PULL 23/49] hw/display/omap_lcdc: Inline template header into C file, Peter Maydell, 2021/03/05
- [PULL 21/49] hw/display/omap_lcdc: Drop broken bigendian ifdef, Peter Maydell, 2021/03/05
- [PULL 24/49] hw/display/omap_lcdc: Delete unnecessary macro, Peter Maydell, 2021/03/05
- [PULL 28/49] hw/arm/mps2-tz: Correct the OSCCLK settings for mps2-an505 and mps2-an511, Peter Maydell, 2021/03/05
- [PULL 32/49] hw/arm/mps2-tz: Make FPGAIO switch and LED config per-board, Peter Maydell, 2021/03/05
- [PULL 31/49] hw/misc/mps2-fpgaio: Support SWITCH register, Peter Maydell, 2021/03/05
- [PULL 26/49] hw/arm/mps2-tz: Make SYSCLK frequency board-specific, Peter Maydell, 2021/03/05
- [PULL 37/49] hw/arm/mps2-tz: Allow PPCPortInfo structures to specify device interrupts, Peter Maydell, 2021/03/05
- [PULL 30/49] hw/misc/mps2-fpgaio: Make number of LEDs configurable by board, Peter Maydell, 2021/03/05
- [PULL 27/49] hw/misc/mps2-scc: Support configurable number of OSCCLK values,
Peter Maydell <=
- [PULL 34/49] hw/arm/mps2-tz: Make number of IRQs board-specific, Peter Maydell, 2021/03/05
- [PULL 35/49] hw/misc/mps2-scc: Implement CFG_REG5 and CFG_REG6 for MPS3 AN524, Peter Maydell, 2021/03/05
- [PULL 46/49] hw/arm/mps2-tz: Stub out USB controller for mps3-an524, Peter Maydell, 2021/03/05
- [PULL 38/49] hw/arm/mps2-tz: Move device IRQ info to data structures, Peter Maydell, 2021/03/05
- [PULL 43/49] hw/arm/mps2-tz: Support ROMs as well as RAMs, Peter Maydell, 2021/03/05
- [PULL 44/49] hw/arm/mps2-tz: Get armv7m_load_kernel() size argument from RAMInfo, Peter Maydell, 2021/03/05
- [PULL 49/49] hw/arm/mps2: Update old infocenter.arm.com URLs, Peter Maydell, 2021/03/05
- [PULL 47/49] hw/arm/mps2-tz: Provide PL031 RTC on mps3-an524, Peter Maydell, 2021/03/05
- [PULL 40/49] hw/arm/mps2-tz: Allow boards to have different PPCInfo data, Peter Maydell, 2021/03/05
- [PULL 45/49] hw/arm/mps2-tz: Add new mps3-an524 board, Peter Maydell, 2021/03/05