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[PULL 17/39] target/arm: Update sve reduction vs simd_desc
From: |
Peter Maydell |
Subject: |
[PULL 17/39] target/arm: Update sve reduction vs simd_desc |
Date: |
Fri, 12 Mar 2021 13:51:18 +0000 |
From: Richard Henderson <richard.henderson@linaro.org>
With the reduction operations, we intentionally increase maxsz to
the next power of 2, so as to fill out the reduction tree correctly.
Since e2e7168a214b, oprsz must equal maxsz, with exceptions for small
vectors, so this triggers an assertion for vector sizes > 32 that are
not themselves a power of 2.
Pass the power-of-two value in the simd_data field instead.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210309155305.11301-9-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/sve_helper.c | 2 +-
target/arm/translate-sve.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 6f4bc3a3cc2..fd6c58f96a8 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -2896,7 +2896,7 @@ static TYPE NAME##_reduce(TYPE *data, float_status
*status, uintptr_t n) \
} \
uint64_t HELPER(NAME)(void *vn, void *vg, void *vs, uint32_t desc) \
{ \
- uintptr_t i, oprsz = simd_oprsz(desc), maxsz = simd_maxsz(desc); \
+ uintptr_t i, oprsz = simd_oprsz(desc), maxsz = simd_data(desc); \
TYPE data[sizeof(ARMVectorReg) / sizeof(TYPE)]; \
for (i = 0; i < oprsz; ) { \
uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3)); \
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 2420cd741b4..0eefb612144 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -3440,7 +3440,7 @@ static void do_reduce(DisasContext *s, arg_rpr_esz *a,
{
unsigned vsz = vec_full_reg_size(s);
unsigned p2vsz = pow2ceil(vsz);
- TCGv_i32 t_desc = tcg_const_i32(simd_desc(vsz, p2vsz, 0));
+ TCGv_i32 t_desc = tcg_const_i32(simd_desc(vsz, vsz, p2vsz));
TCGv_ptr t_zn, t_pg, status;
TCGv_i64 temp;
--
2.20.1
- [PULL 25/39] hw/arm/virt: KVM: The IPA lower bound is 32, (continued)
- [PULL 25/39] hw/arm/virt: KVM: The IPA lower bound is 32, Peter Maydell, 2021/03/12
- [PULL 22/39] tests/acceptance: drop ARMBIAN_ARTIFACTS_CACHED condition for orangepi-pc, cubieboard tests, Peter Maydell, 2021/03/12
- [PULL 30/39] tests/qtest: Test PWM fan RPM using MFT in PWM test, Peter Maydell, 2021/03/12
- [PULL 31/39] hw/display/pl110: Remove dead code for non-32-bpp surfaces, Peter Maydell, 2021/03/12
- [PULL 32/39] hw/display/pl110: Pull included-once parts of template header into pl110.c, Peter Maydell, 2021/03/12
- [PULL 28/39] hw/arm: Add MFT device to NPCM7xx Soc, Peter Maydell, 2021/03/12
- [PULL 33/39] hw/display/pl110: Remove use of BITS from pl110_template.h, Peter Maydell, 2021/03/12
- [PULL 37/39] hw/display/pxa2xx: Apply brace-related coding style fixes to template header, Peter Maydell, 2021/03/12
- [PULL 38/39] hw/display/pxa2xx: Apply whitespace-only coding style fixes to template header, Peter Maydell, 2021/03/12
- [PULL 39/39] hw/display/pxa2xx: Inline template header, Peter Maydell, 2021/03/12
- [PULL 17/39] target/arm: Update sve reduction vs simd_desc,
Peter Maydell <=
- [PULL 36/39] hw/display/pxa2xx: Remove use of BITS in pxa2xx_template.h, Peter Maydell, 2021/03/12