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[PULL 03/27] hw/mips/gt64xxx: Fix typos in qemu_log_mask() formats
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From: |
Philippe Mathieu-Daudé |
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Subject: |
[PULL 03/27] hw/mips/gt64xxx: Fix typos in qemu_log_mask() formats |
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Date: |
Sat, 13 Mar 2021 20:48:05 +0100 |
Fix the following typos:
- GT_PCI1_CFGDATA is not a timer register but a PCI one,
- zero-padding flag is out of the format
Fixes: 641ca2bfcd5 ("hw/mips/gt64xxx_pci: Use qemu_log_mask() instead of debug
printf()")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20210309142630.728014-4-f4bug@amsat.org>
---
hw/mips/gt64xxx_pci.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
index 99b1690af19..8ff31380d74 100644
--- a/hw/mips/gt64xxx_pci.c
+++ b/hw/mips/gt64xxx_pci.c
@@ -463,7 +463,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
/* Read-only registers, do nothing */
qemu_log_mask(LOG_GUEST_ERROR,
"gt64120: Read-only register write "
- "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
+ "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break;
@@ -473,7 +473,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
/* Read-only registers, do nothing */
qemu_log_mask(LOG_GUEST_ERROR,
"gt64120: Read-only register write "
- "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
+ "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break;
@@ -515,7 +515,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
/* Not implemented */
qemu_log_mask(LOG_UNIMP,
"gt64120: Unimplemented device register write "
- "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
+ "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break;
@@ -528,7 +528,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
/* Read-only registers, do nothing */
qemu_log_mask(LOG_GUEST_ERROR,
"gt64120: Read-only register write "
- "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
+ "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break;
@@ -565,7 +565,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
/* Not implemented */
qemu_log_mask(LOG_UNIMP,
"gt64120: Unimplemented DMA register write "
- "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
+ "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break;
@@ -578,7 +578,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
/* Not implemented */
qemu_log_mask(LOG_UNIMP,
"gt64120: Unimplemented timer register write "
- "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
+ "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break;
@@ -621,8 +621,8 @@ static void gt64120_writel(void *opaque, hwaddr addr,
case GT_PCI1_CFGDATA:
/* not implemented */
qemu_log_mask(LOG_UNIMP,
- "gt64120: Unimplemented timer register write "
- "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
+ "gt64120: Unimplemented PCI register write "
+ "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break;
case GT_PCI0_CFGADDR:
@@ -682,7 +682,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
default:
qemu_log_mask(LOG_GUEST_ERROR,
"gt64120: Illegal register write "
- "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
+ "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break;
}
@@ -958,7 +958,7 @@ static uint64_t gt64120_readl(void *opaque,
val = s->regs[saddr];
qemu_log_mask(LOG_GUEST_ERROR,
"gt64120: Illegal register read "
- "reg:0x03%x size:%u value:0x%0*x\n",
+ "reg:0x%03x size:%u value:0x%0*x\n",
saddr << 2, size, size << 1, val);
break;
}
--
2.26.2
- [PULL 00/27] MIPS patches for 2021-03-13, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 01/27] hw/mips/gt64xxx: Initialize ISD I/O memory region in DeviceRealize(), Philippe Mathieu-Daudé, 2021/03/13
- [PULL 02/27] hw/mips/gt64xxx: Simplify ISD MemoryRegion read/write handlers, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 03/27] hw/mips/gt64xxx: Fix typos in qemu_log_mask() formats,
Philippe Mathieu-Daudé <=
- [PULL 04/27] hw/mips/gt64xxx: Rename trace events related to interrupt registers, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 05/27] hw/mips/gt64xxx: Trace accesses to ISD registers, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 06/27] target/mips/meson: Introduce mips_tcg source set, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 07/27] target/mips/meson: Restrict mips-semi.c to TCG, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 08/27] target/mips: Rewrite complex ifdef'ry, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 09/27] target/mips: Remove XBurst Media eXtension Unit dead code, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 10/27] target/mips: Remove unused CPUMIPSState* from MXU functions, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 11/27] target/mips: Pass instruction opcode to decode_opc_mxu(), Philippe Mathieu-Daudé, 2021/03/13
- [PULL 12/27] target/mips: Use OPC_MUL instead of OPC__MXU_MUL, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 13/27] target/mips: Move MUL opcode check from decode_mxu() to decode_legacy(), Philippe Mathieu-Daudé, 2021/03/13