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[PULL 25/27] target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetre
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 25/27] target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree |
Date: |
Sat, 13 Mar 2021 20:48:27 +0100 |
Move PCPYLD (Parallel Copy Lower Doubleword) and PCPYUD
(Parallel Copy Upper Doubleword) to decodetree. Remove
unnecessary code / comments.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210214175912.732946-13-f4bug@amsat.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
v2: Use gen_load_gpr_hi (rth)
---
target/mips/tx79.decode | 6 +++
target/mips/translate.c | 80 ------------------------------------
target/mips/tx79_translate.c | 42 +++++++++++++++++++
3 files changed, 48 insertions(+), 80 deletions(-)
diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
index 7af35458b0a..0f748b53a64 100644
--- a/target/mips/tx79.decode
+++ b/target/mips/tx79.decode
@@ -17,6 +17,7 @@
# Named instruction formats. These are generally used to
# reduce the amount of duplication between instruction patterns.
+@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &rtype sa=0
@rt_rd ...... ..... rt:5 rd:5 ..... ...... &rtype rs=0 sa=0
@rs ...... rs:5 ..... .......... ...... &rtype rt=0 rd=0 sa=0
@rd ...... .......... rd:5 ..... ...... &rtype rs=0 rt=0 sa=0
@@ -28,6 +29,11 @@ MTHI1 011100 ..... 0000000000 00000 010001 @rs
MFLO1 011100 0000000000 ..... 00000 010010 @rd
MTLO1 011100 ..... 0000000000 00000 010011 @rs
+# MMI2
+
+PCPYLD 011100 ..... ..... ..... 01110 001001 @rs_rt_rd
+
# MMI3
+PCPYUD 011100 ..... ..... ..... 01110 101001 @rs_rt_rd
PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 80fcab5a564..08e4995c730 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24062,80 +24062,6 @@ static void decode_opc_special(CPUMIPSState *env,
DisasContext *ctx)
* PEXTUW
*/
-/*
- * PCPYLD rd, rs, rt
- *
- * Parallel Copy Lower Doubleword
- *
- * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-----------+---------+---------+---------+---------+-----------+
- * | MMI | rs | rt | rd | PCPYLD | MMI2 |
- * +-----------+---------+---------+---------+---------+-----------+
- */
-static void gen_mmi_pcpyld(DisasContext *ctx)
-{
- uint32_t rs, rt, rd;
- uint32_t opcode;
-
- opcode = ctx->opcode;
-
- rs = extract32(opcode, 21, 5);
- rt = extract32(opcode, 16, 5);
- rd = extract32(opcode, 11, 5);
-
- if (rd == 0) {
- /* nop */
- } else {
- if (rs == 0) {
- tcg_gen_movi_i64(cpu_gpr_hi[rd], 0);
- } else {
- tcg_gen_mov_i64(cpu_gpr_hi[rd], cpu_gpr[rs]);
- }
- if (rt == 0) {
- tcg_gen_movi_i64(cpu_gpr[rd], 0);
- } else {
- if (rd != rt) {
- tcg_gen_mov_i64(cpu_gpr[rd], cpu_gpr[rt]);
- }
- }
- }
-}
-
-/*
- * PCPYUD rd, rs, rt
- *
- * Parallel Copy Upper Doubleword
- *
- * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-----------+---------+---------+---------+---------+-----------+
- * | MMI | rs | rt | rd | PCPYUD | MMI3 |
- * +-----------+---------+---------+---------+---------+-----------+
- */
-static void gen_mmi_pcpyud(DisasContext *ctx)
-{
- uint32_t rs, rt, rd;
- uint32_t opcode;
-
- opcode = ctx->opcode;
-
- rs = extract32(opcode, 21, 5);
- rt = extract32(opcode, 16, 5);
- rd = extract32(opcode, 11, 5);
-
- if (rd == 0) {
- /* nop */
- } else {
- gen_load_gpr_hi(cpu_gpr[rd], rs);
- if (rt == 0) {
- tcg_gen_movi_i64(cpu_gpr_hi[rd], 0);
- } else {
- if (rd != rt) {
- tcg_gen_mov_i64(cpu_gpr_hi[rd], cpu_gpr_hi[rt]);
- }
- }
- }
-}
-
#endif
static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
@@ -24952,9 +24878,6 @@ static void decode_mmi2(CPUMIPSState *env, DisasContext
*ctx)
case MMI_OPC_2_PROT3W: /* TODO: MMI_OPC_2_PROT3W */
gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI2 */
break;
- case MMI_OPC_2_PCPYLD:
- gen_mmi_pcpyld(ctx);
- break;
default:
MIPS_INVAL("TX79 MMI class MMI2");
gen_reserved_instruction(ctx);
@@ -24980,9 +24903,6 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext
*ctx)
case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */
gen_reserved_instruction(ctx); /* TODO: MMI_OPC_CLASS_MMI3 */
break;
- case MMI_OPC_3_PCPYUD:
- gen_mmi_pcpyud(ctx);
- break;
default:
MIPS_INVAL("TX79 MMI class MMI3");
gen_reserved_instruction(ctx);
diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
index d58b4fcd7b3..6e90eb64608 100644
--- a/target/mips/tx79_translate.c
+++ b/target/mips/tx79_translate.c
@@ -71,3 +71,45 @@ static bool trans_PCPYH(DisasContext *s, arg_rtype *a)
return true;
}
+
+/* Parallel Copy Lower Doubleword */
+static bool trans_PCPYLD(DisasContext *s, arg_rtype *a)
+{
+ if (a->rd == 0) {
+ /* nop */
+ return true;
+ }
+
+ if (a->rs == 0) {
+ tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
+ } else {
+ tcg_gen_mov_i64(cpu_gpr_hi[a->rd], cpu_gpr[a->rs]);
+ }
+
+ if (a->rt == 0) {
+ tcg_gen_movi_i64(cpu_gpr[a->rd], 0);
+ } else if (a->rd != a->rt) {
+ tcg_gen_mov_i64(cpu_gpr[a->rd], cpu_gpr[a->rt]);
+ }
+
+ return true;
+}
+
+/* Parallel Copy Upper Doubleword */
+static bool trans_PCPYUD(DisasContext *s, arg_rtype *a)
+{
+ if (a->rd == 0) {
+ /* nop */
+ return true;
+ }
+
+ gen_load_gpr_hi(cpu_gpr[a->rd], a->rs);
+
+ if (a->rt == 0) {
+ tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
+ } else if (a->rd != a->rt) {
+ tcg_gen_mov_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rt]);
+ }
+
+ return true;
+}
--
2.26.2
- [PULL 15/27] target/mips: Convert decode_ase_mxu() to decodetree prototype, (continued)
- [PULL 15/27] target/mips: Convert decode_ase_mxu() to decodetree prototype, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 16/27] target/mips: Simplify decode_opc_mxu() ifdef'ry, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 17/27] target/mips: Introduce mxu_translate_init() helper, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 18/27] target/mips: Extract MXU code to new mxu_translate.c file, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 19/27] target/mips: Use gen_load_gpr[_hi]() when possible, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 21/27] target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetree, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 20/27] target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 22/27] target/mips/translate: Make gen_rdhwr() public, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 23/27] target/mips/translate: Simplify PCPYH using deposit_i64(), Philippe Mathieu-Daudé, 2021/03/13
- [PULL 24/27] target/mips/tx79: Move PCPYH opcode to decodetree, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 25/27] target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree,
Philippe Mathieu-Daudé <=
- [PULL 26/27] target/mips: Remove 'C790 Multimedia Instructions' dead code, Philippe Mathieu-Daudé, 2021/03/13
- [PULL 27/27] target/mips/tx79: Salvage instructions description comment, Philippe Mathieu-Daudé, 2021/03/13
- Re: [PULL 00/27] MIPS patches for 2021-03-13, Peter Maydell, 2021/03/15