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[PULL 04/16] target/riscv: add log of PMP permission checking
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From: |
Alistair Francis |
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Subject: |
[PULL 04/16] target/riscv: add log of PMP permission checking |
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Date: |
Mon, 22 Mar 2021 21:57:44 -0400 |
From: Jim Shu <cwshu@andestech.com>
Like MMU translation, add qemu log of PMP permission checking for
debugging.
Signed-off-by: Jim Shu <cwshu@andestech.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1613916082-19528-3-git-send-email-cwshu@andestech.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index fa385594df..0515f9aec8 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -794,6 +794,12 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
if (ret == TRANSLATE_SUCCESS) {
ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
size, access_type, mode);
+
+ qemu_log_mask(CPU_LOG_MMU,
+ "%s PMP address=" TARGET_FMT_plx " ret %d prot"
+ " %d tlb_size " TARGET_FMT_lu "\n",
+ __func__, pa, ret, prot_pmp, tlb_size);
+
prot &= prot_pmp;
}
@@ -821,6 +827,12 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
if (ret == TRANSLATE_SUCCESS) {
ret = get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa,
size, access_type, mode);
+
+ qemu_log_mask(CPU_LOG_MMU,
+ "%s PMP address=" TARGET_FMT_plx " ret %d prot"
+ " %d tlb_size " TARGET_FMT_lu "\n",
+ __func__, pa, ret, prot_pmp, tlb_size);
+
prot &= prot_pmp;
}
}
--
2.30.1
- [PULL 00/16] riscv-to-apply queue, Alistair Francis, 2021/03/22
- [PULL 01/16] target/riscv: fix vs() to return proper error code, Alistair Francis, 2021/03/22
- [PULL 02/16] hw/char: disable ibex uart receive if the buffer is full, Alistair Francis, 2021/03/22
- [PULL 03/16] target/riscv: propagate PMP permission to TLB page, Alistair Francis, 2021/03/22
- [PULL 05/16] target/riscv: flush TLB pages if PMP permission has been changed, Alistair Francis, 2021/03/22
- [PULL 04/16] target/riscv: add log of PMP permission checking,
Alistair Francis <=
- [PULL 06/16] target/riscv: Adjust privilege level for HLV(X)/HSV instructions, Alistair Francis, 2021/03/22
- [PULL 08/16] target/riscv: Use background registers also for MSTATUS_MPV, Alistair Francis, 2021/03/22
- [PULL 07/16] target/riscv: Make VSTIP and VSEIP read-only in hip, Alistair Francis, 2021/03/22
- [PULL 09/16] hw/riscv: Add fw_cfg support to virt, Alistair Francis, 2021/03/22
- [PULL 10/16] hw/riscv: allow ramfb on virt, Alistair Francis, 2021/03/22
- [PULL 11/16] target/riscv: Fix read and write accesses to vsip and vsie, Alistair Francis, 2021/03/22
- [PULL 12/16] target/riscv: Add proper two-stage lookup exception detection, Alistair Francis, 2021/03/22
- [PULL 13/16] hw/block: m25p80: Support fast read for SST flashes, Alistair Francis, 2021/03/22
- [PULL 14/16] hw/riscv: microchip_pfsoc: Map EMMC/SD mux register, Alistair Francis, 2021/03/22
- [PULL 15/16] docs/system: riscv: Add documentation for 'microchip-icicle-kit' machine, Alistair Francis, 2021/03/22