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[RFC PATCH 09/11] target/riscv: Update CSR mclicbase in CLIC mode
From: |
LIU Zhiwei |
Subject: |
[RFC PATCH 09/11] target/riscv: Update CSR mclicbase in CLIC mode |
Date: |
Fri, 9 Apr 2021 15:48:55 +0800 |
The machine mode mclicbase CSR is an XLEN-bit read-only register providing
the base address of CLIC memory mapped registers.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
hw/intc/riscv_clic.c | 1 +
target/riscv/cpu.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/hw/intc/riscv_clic.c b/hw/intc/riscv_clic.c
index 8ad534c506..e902dd4062 100644
--- a/hw/intc/riscv_clic.c
+++ b/hw/intc/riscv_clic.c
@@ -715,6 +715,7 @@ static void riscv_clic_realize(DeviceState *dev, Error
**errp)
&cpu->env, 1);
qdev_connect_gpio_out(dev, i, irq);
cpu->env.clic = clic;
+ cpu->env.mclicbase = clic->mclicbase;
}
}
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index b5fd796f98..b0b8565649 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -162,6 +162,7 @@ struct CPURISCVState {
uint32_t miclaim;
uint32_t mintstatus; /* clic-spec */
target_ulong mintthresh; /* clic-spec */
+ target_ulong mclicbase; /* clic-spec */
target_ulong mie;
target_ulong mideleg;
--
2.25.1
- [RFC PATCH 00/11] RISC-V: support clic v0.9 specification, LIU Zhiwei, 2021/04/09
- [RFC PATCH 04/11] target/riscv: Update CSR xie in CLIC mode, LIU Zhiwei, 2021/04/09
- [RFC PATCH 08/11] target/riscv: Update CSR xnxti in CLIC mode, LIU Zhiwei, 2021/04/09
- [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus, LIU Zhiwei, 2021/04/09
- [RFC PATCH 05/11] target/riscv: Update CSR xip in CLIC mode, LIU Zhiwei, 2021/04/09
- [RFC PATCH 09/11] target/riscv: Update CSR mclicbase in CLIC mode,
LIU Zhiwei <=
- [RFC PATCH 06/11] target/riscv: Update CSR xtvec in CLIC mode, LIU Zhiwei, 2021/04/09
- [RFC PATCH 10/11] target/riscv: Update interrupt handling in CLIC mode, LIU Zhiwei, 2021/04/09
- [RFC PATCH 07/11] target/riscv: Update CSR xtvt in CLIC mode, LIU Zhiwei, 2021/04/09
- [RFC PATCH 02/11] target/riscv: Update CSR xintthresh in CLIC mode, LIU Zhiwei, 2021/04/09
- [RFC PATCH 11/11] target/riscv: Update interrupt return in CLIC mode, LIU Zhiwei, 2021/04/09
- [RFC PATCH 03/11] hw/intc: Add CLIC device, LIU Zhiwei, 2021/04/09
- Re: [RFC PATCH 00/11] RISC-V: support clic v0.9 specification, Alistair Francis, 2021/04/19