[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v2 3/9] target/riscv: Remove the hardcoded HGATP_MODE macro
From: |
Alistair Francis |
Subject: |
[PATCH v2 3/9] target/riscv: Remove the hardcoded HGATP_MODE macro |
Date: |
Wed, 14 Apr 2021 09:33:36 +1000 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu_bits.h | 11 -----------
target/riscv/cpu_helper.c | 24 +++++++++++++++---------
2 files changed, 15 insertions(+), 20 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 969dd05eae..8caab23b62 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -207,17 +207,6 @@
#define CSR_HTIMEDELTA 0x605
#define CSR_HTIMEDELTAH 0x615
-#if defined(TARGET_RISCV32)
-#define HGATP_MODE SATP32_MODE
-#define HGATP_VMID SATP32_ASID
-#define HGATP_PPN SATP32_PPN
-#endif
-#if defined(TARGET_RISCV64)
-#define HGATP_MODE SATP64_MODE
-#define HGATP_VMID SATP64_ASID
-#define HGATP_PPN SATP64_PPN
-#endif
-
/* Virtual CSRs */
#define CSR_VSSTATUS 0x200
#define CSR_VSIE 0x204
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 21c54ef561..b065ddb681 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -411,8 +411,13 @@ static int get_physical_address(CPURISCVState *env, hwaddr
*physical,
}
widened = 0;
} else {
- base = (hwaddr)get_field(env->hgatp, HGATP_PPN) << PGSHIFT;
- vm = get_field(env->hgatp, HGATP_MODE);
+ if (riscv_cpu_is_32bit(env)) {
+ base = (hwaddr)get_field(env->hgatp, SATP32_PPN) << PGSHIFT;
+ vm = get_field(env->hgatp, SATP32_MODE);
+ } else {
+ base = (hwaddr)get_field(env->hgatp, SATP64_PPN) << PGSHIFT;
+ vm = get_field(env->hgatp, SATP64_MODE);
+ }
widened = 2;
}
/* status.SUM will be ignored if execute on background */
@@ -615,16 +620,17 @@ static void raise_mmu_exception(CPURISCVState *env,
target_ulong address,
bool first_stage, bool two_stage)
{
CPUState *cs = env_cpu(env);
- int page_fault_exceptions;
+ int page_fault_exceptions, vm;
+
if (first_stage) {
- page_fault_exceptions =
- get_field(env->satp, SATP_MODE) != VM_1_10_MBARE &&
- !pmp_violation;
+ vm = get_field(env->satp, SATP_MODE);
+ } else if (riscv_cpu_is_32bit(env)) {
+ vm = get_field(env->hgatp, SATP32_MODE);
} else {
- page_fault_exceptions =
- get_field(env->hgatp, HGATP_MODE) != VM_1_10_MBARE &&
- !pmp_violation;
+ vm = get_field(env->hgatp, SATP64_MODE);
}
+ page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation;
+
switch (access_type) {
case MMU_INST_FETCH:
if (riscv_cpu_virt_enabled(env) && !first_stage) {
--
2.31.1
- [PATCH v2 0/9] RISC-V: Steps towards running 32-bit guests on, Alistair Francis, 2021/04/13
- [PATCH v2 2/9] target/riscv: Remove the hardcoded SSTATUS_SD macro, Alistair Francis, 2021/04/13
- [PATCH v2 1/9] target/riscv: Remove the hardcoded RVXLEN macro, Alistair Francis, 2021/04/13
- [PATCH v2 3/9] target/riscv: Remove the hardcoded HGATP_MODE macro,
Alistair Francis <=
- [PATCH v2 5/9] target/riscv: Remove the hardcoded SATP_MODE macro, Alistair Francis, 2021/04/13
- [PATCH v2 6/9] target/riscv: Remove the unused HSTATUS_WPRI macro, Alistair Francis, 2021/04/13
- [PATCH v2 8/9] target/riscv: Consolidate RV32/64 32-bit instructions, Alistair Francis, 2021/04/13
- [PATCH v2 7/9] target/riscv: Remove an unused CASE_OP_32_64 macro, Alistair Francis, 2021/04/13