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[RFC v13 20/80] target/arm: move arm_hcr_el2_eff from tcg/ to common_cpu
From: |
Claudio Fontana |
Subject: |
[RFC v13 20/80] target/arm: move arm_hcr_el2_eff from tcg/ to common_cpu |
Date: |
Wed, 14 Apr 2021 13:25:50 +0200 |
we will need this for KVM too, especially for Nested support.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu-common.c | 68 +++++++++++++++++++++++++++++++++++++++++
target/arm/tcg/helper.c | 68 -----------------------------------------
2 files changed, 68 insertions(+), 68 deletions(-)
diff --git a/target/arm/cpu-common.c b/target/arm/cpu-common.c
index 694e5d73f3..040e06392a 100644
--- a/target/arm/cpu-common.c
+++ b/target/arm/cpu-common.c
@@ -231,3 +231,71 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t
mask,
mask &= ~CACHED_CPSR_BITS;
env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
}
+
+/*
+ * Return the effective value of HCR_EL2.
+ * Bits that are not included here:
+ * RW (read from SCR_EL3.RW as needed)
+ */
+uint64_t arm_hcr_el2_eff(CPUARMState *env)
+{
+ uint64_t ret = env->cp15.hcr_el2;
+
+ if (!arm_is_el2_enabled(env)) {
+ /*
+ * "This register has no effect if EL2 is not enabled in the
+ * current Security state". This is ARMv8.4-SecEL2 speak for
+ * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
+ *
+ * Prior to that, the language was "In an implementation that
+ * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
+ * as if this field is 0 for all purposes other than a direct
+ * read or write access of HCR_EL2". With lots of enumeration
+ * on a per-field basis. In current QEMU, this is condition
+ * is arm_is_secure_below_el3.
+ *
+ * Since the v8.4 language applies to the entire register, and
+ * appears to be backward compatible, use that.
+ */
+ return 0;
+ }
+
+ /*
+ * For a cpu that supports both aarch64 and aarch32, we can set bits
+ * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32.
+ * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32.
+ */
+ if (!arm_el_is_aa64(env, 2)) {
+ uint64_t aa32_valid;
+
+ /*
+ * These bits are up-to-date as of ARMv8.6.
+ * For HCR, it's easiest to list just the 2 bits that are invalid.
+ * For HCR2, list those that are valid.
+ */
+ aa32_valid = MAKE_64BIT_MASK(0, 32) & ~(HCR_RW | HCR_TDZ);
+ aa32_valid |= (HCR_CD | HCR_ID | HCR_TERR | HCR_TEA | HCR_MIOCNCE |
+ HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_TTLBIS);
+ ret &= aa32_valid;
+ }
+
+ if (ret & HCR_TGE) {
+ /* These bits are up-to-date as of ARMv8.6. */
+ if (ret & HCR_E2H) {
+ ret &= ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO |
+ HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE |
+ HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU |
+ HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE |
+ HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_ENSCXT |
+ HCR_TTLBIS | HCR_TTLBOS | HCR_TID5);
+ } else {
+ ret |= HCR_FMO | HCR_IMO | HCR_AMO;
+ }
+ ret &= ~(HCR_SWIO | HCR_PTW | HCR_VF | HCR_VI | HCR_VSE |
+ HCR_FB | HCR_TID1 | HCR_TID3 | HCR_TSC | HCR_TACR |
+ HCR_TSW | HCR_TTLB | HCR_TVM | HCR_HCD | HCR_TRVM |
+ HCR_TLOR);
+ }
+
+ return ret;
+}
diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c
index f35d2969b0..15f53d57b0 100644
--- a/target/arm/tcg/helper.c
+++ b/target/arm/tcg/helper.c
@@ -261,74 +261,6 @@ static int arm_gdb_set_svereg(CPUARMState *env, uint8_t
*buf, int reg)
}
#endif /* TARGET_AARCH64 */
-/*
- * Return the effective value of HCR_EL2.
- * Bits that are not included here:
- * RW (read from SCR_EL3.RW as needed)
- */
-uint64_t arm_hcr_el2_eff(CPUARMState *env)
-{
- uint64_t ret = env->cp15.hcr_el2;
-
- if (!arm_is_el2_enabled(env)) {
- /*
- * "This register has no effect if EL2 is not enabled in the
- * current Security state". This is ARMv8.4-SecEL2 speak for
- * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
- *
- * Prior to that, the language was "In an implementation that
- * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
- * as if this field is 0 for all purposes other than a direct
- * read or write access of HCR_EL2". With lots of enumeration
- * on a per-field basis. In current QEMU, this is condition
- * is arm_is_secure_below_el3.
- *
- * Since the v8.4 language applies to the entire register, and
- * appears to be backward compatible, use that.
- */
- return 0;
- }
-
- /*
- * For a cpu that supports both aarch64 and aarch32, we can set bits
- * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32.
- * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32.
- */
- if (!arm_el_is_aa64(env, 2)) {
- uint64_t aa32_valid;
-
- /*
- * These bits are up-to-date as of ARMv8.6.
- * For HCR, it's easiest to list just the 2 bits that are invalid.
- * For HCR2, list those that are valid.
- */
- aa32_valid = MAKE_64BIT_MASK(0, 32) & ~(HCR_RW | HCR_TDZ);
- aa32_valid |= (HCR_CD | HCR_ID | HCR_TERR | HCR_TEA | HCR_MIOCNCE |
- HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_TTLBIS);
- ret &= aa32_valid;
- }
-
- if (ret & HCR_TGE) {
- /* These bits are up-to-date as of ARMv8.6. */
- if (ret & HCR_E2H) {
- ret &= ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO |
- HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE |
- HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU |
- HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE |
- HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_ENSCXT |
- HCR_TTLBIS | HCR_TTLBOS | HCR_TID5);
- } else {
- ret |= HCR_FMO | HCR_IMO | HCR_AMO;
- }
- ret &= ~(HCR_SWIO | HCR_PTW | HCR_VF | HCR_VI | HCR_VSE |
- HCR_FB | HCR_TID1 | HCR_TID3 | HCR_TSC | HCR_TACR |
- HCR_TSW | HCR_TTLB | HCR_TVM | HCR_HCD | HCR_TRVM |
- HCR_TLOR);
- }
-
- return ret;
-}
-
/* Return the exception level to which exceptions should be taken
* via SVEAccessTrap. If an exception should be routed through
* AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should
--
2.26.2
- [RFC v13 09/80] target/arm: only build psci for TCG, (continued)
- [RFC v13 09/80] target/arm: only build psci for TCG, Claudio Fontana, 2021/04/14
- [RFC v13 08/80] target/arm: tcg: split m_helper user-only and sysemu-only parts, Claudio Fontana, 2021/04/14
- [RFC v13 15/80] target/arm: move cpu definitions to common cpu module, Claudio Fontana, 2021/04/14
- [RFC v13 11/80] target/arm: tcg: fix comment style before move to cpu-mmu, Claudio Fontana, 2021/04/14
- [RFC v13 12/80] target/arm: move physical address translation to cpu-mmu, Claudio Fontana, 2021/04/14
- [RFC v13 17/80] target/arm: tcg: add stubs for some helpers for non-tcg builds, Claudio Fontana, 2021/04/14
- [RFC v13 13/80] target/arm: fix style in preparation of new cpregs module, Claudio Fontana, 2021/04/14
- [RFC v13 16/80] target/arm: only perform TCG cpu and machine inits if TCG enabled, Claudio Fontana, 2021/04/14
- [RFC v13 19/80] target/arm: add temporary stub for arm_rebuild_hflags, Claudio Fontana, 2021/04/14
- [RFC v13 18/80] target/arm: move cpsr_read, cpsr_write to cpu_common, Claudio Fontana, 2021/04/14
- [RFC v13 20/80] target/arm: move arm_hcr_el2_eff from tcg/ to common_cpu,
Claudio Fontana <=
- [RFC v13 21/80] target/arm: split vfp state setting from tcg helpers, Claudio Fontana, 2021/04/14
- [RFC v13 22/80] target/arm: move arm_mmu_idx* to cpu-mmu, Claudio Fontana, 2021/04/14
- [RFC v13 25/80] target/arm: move arm_cpu_list to common_cpu, Claudio Fontana, 2021/04/14
- [RFC v13 27/80] target/arm: new cpu32 ARM 32 bit CPU Class, Claudio Fontana, 2021/04/14
- [RFC v13 14/80] target/arm: split cpregs from tcg/helper.c, Claudio Fontana, 2021/04/14
- [RFC v13 23/80] target/arm: move sve_zcr_len_for_el to common_cpu, Claudio Fontana, 2021/04/14
- [RFC v13 24/80] target/arm: move arm_sctlr away from tcg helpers, Claudio Fontana, 2021/04/14
- [RFC v13 28/80] target/arm: split 32bit and 64bit arm dump state, Claudio Fontana, 2021/04/14
- [RFC v13 33/80] target/arm: move fp_exception_el out of TCG helpers, Claudio Fontana, 2021/04/14
- [RFC v13 31/80] target/arm: move sve_exception_el out of TCG helpers, Claudio Fontana, 2021/04/14