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[RFC v13 39/80] target/arm: replace CONFIG_TCG with tcg_enabled
From: |
Claudio Fontana |
Subject: |
[RFC v13 39/80] target/arm: replace CONFIG_TCG with tcg_enabled |
Date: |
Wed, 14 Apr 2021 13:26:09 +0200 |
for "all" builds (tcg + kvm), we want to avoid doing
the psci and semihosting checks if tcg is built-in, but not enabled.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
target/arm/cpu-sysemu.c | 30 +++++++++++++++---------------
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/target/arm/cpu-sysemu.c b/target/arm/cpu-sysemu.c
index 7569241339..e83d55b9f7 100644
--- a/target/arm/cpu-sysemu.c
+++ b/target/arm/cpu-sysemu.c
@@ -1141,22 +1141,22 @@ void arm_cpu_do_interrupt(CPUState *cs)
env->exception.syndrome);
}
-#ifdef CONFIG_TCG
- if (arm_is_psci_call(cpu, cs->exception_index)) {
- arm_handle_psci_call(cpu);
- qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
- return;
- }
- /*
- * Semihosting semantics depend on the register width of the code
- * that caused the exception, not the target exception level, so
- * must be handled here.
- */
- if (cs->exception_index == EXCP_SEMIHOST) {
- tcg_handle_semihosting(cs);
- return;
+ if (tcg_enabled()) {
+ if (arm_is_psci_call(cpu, cs->exception_index)) {
+ arm_handle_psci_call(cpu);
+ qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
+ return;
+ }
+ /*
+ * Semihosting semantics depend on the register width of the code
+ * that caused the exception, not the target exception level, so
+ * must be handled here.
+ */
+ if (cs->exception_index == EXCP_SEMIHOST) {
+ tcg_handle_semihosting(cs);
+ return;
+ }
}
-#endif /* CONFIG_TCG */
/*
* Hooks may change global state so BQL should be held, also the
* BQL needs to be held for any modification of
--
2.26.2
- [RFC v13 27/80] target/arm: new cpu32 ARM 32 bit CPU Class, (continued)
- [RFC v13 27/80] target/arm: new cpu32 ARM 32 bit CPU Class, Claudio Fontana, 2021/04/14
- [RFC v13 14/80] target/arm: split cpregs from tcg/helper.c, Claudio Fontana, 2021/04/14
- [RFC v13 23/80] target/arm: move sve_zcr_len_for_el to common_cpu, Claudio Fontana, 2021/04/14
- [RFC v13 24/80] target/arm: move arm_sctlr away from tcg helpers, Claudio Fontana, 2021/04/14
- [RFC v13 28/80] target/arm: split 32bit and 64bit arm dump state, Claudio Fontana, 2021/04/14
- [RFC v13 33/80] target/arm: move fp_exception_el out of TCG helpers, Claudio Fontana, 2021/04/14
- [RFC v13 31/80] target/arm: move sve_exception_el out of TCG helpers, Claudio Fontana, 2021/04/14
- [RFC v13 36/80] target/arm: fix style of arm_cpu_do_interrupt functions before move, Claudio Fontana, 2021/04/14
- [RFC v13 42/80] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled(), Claudio Fontana, 2021/04/14
- [RFC v13 40/80] target/arm: move TCGCPUOps to tcg/tcg-cpu.c, Claudio Fontana, 2021/04/14
- [RFC v13 39/80] target/arm: replace CONFIG_TCG with tcg_enabled,
Claudio Fontana <=
- [RFC v13 44/80] target/arm: move kvm-const.h, kvm.c, kvm64.c, kvm_arm.h to kvm/, Claudio Fontana, 2021/04/14
- [RFC v13 26/80] target/arm: move aarch64_sync_32_to_64 (and vv) to cpu code, Claudio Fontana, 2021/04/14
- [RFC v13 35/80] target/arm: make further preparation for the exception code to move, Claudio Fontana, 2021/04/14
- [RFC v13 43/80] target/arm: remove kvm include file for PSCI and arm-powerctl, Claudio Fontana, 2021/04/14
- [RFC v13 46/80] target/arm: cleanup cpu includes, Claudio Fontana, 2021/04/14
- [RFC v13 48/80] target/arm: remove kvm-stub.c, Claudio Fontana, 2021/04/14
- [RFC v13 30/80] target/arm: fixup sve_exception_el code style before move, Claudio Fontana, 2021/04/14
- [RFC v13 32/80] target/arm: fix comments style of fp_exception_el before moving it, Claudio Fontana, 2021/04/14
- [RFC v13 38/80] target/arm: rename handle_semihosting to tcg_handle_semihosting, Claudio Fontana, 2021/04/14
- [RFC v13 45/80] MAINTAINERS: update arm kvm maintained files to all in target/arm/kvm/, Claudio Fontana, 2021/04/14