Re: [Bug 1923629] [NEW] RISC-V Vector Instruction vssub.vv not saturating

[Alistair Francis]

On Thu, Apr 15, 2021 at 2:18 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> Hi Alistair,
>
> I think that this bug has been resolved in my packed-extension patch set[1].
>
> Would you mind to have a test and merge it before the whole patch set?

Great! Thanks

I have applied patch 3 for the next PR.

Alistair

>
> Thanks.
>
>
> Best Regards,
>
> Zhiwei
>
> [1]: https://www.mail-archive.com/qemu-devel@nongnu.org/msg782125.html
>
>
>
> On 2021/4/15 上午11:57, Alistair Francis wrote:
> > + LIU Zhiwei and Kito Cheng
> >
> > Alistair
> >
> > On Wed, Apr 14, 2021 at 1:31 AM Tony Cole <1923629@bugs.launchpad.net> 
> > wrote:
> >> Public bug reported:
> >>
> >> I noticed doing a negate ( 0 – 0x80000000 ) using vssub.vv produces an
> >> incorrect result of 0x80000000 (should saturate to 0x7FFFFFFF).
> >>
> >> Here is the bit of the code:
> >>
> >>                  vmv.v.i         v16, 0
> >>                  …
> >> 8f040457        vssub.vv        v8,v16,v8
> >>
> >> I believe the instruction encoding is correct (vssub.vv with vd = v8,
> >> vs2 = v16, rs1 = v8), but the result does not saturate in QEMU.
> >>
> >> I’ve just tested with what I think is the latest branch (
> >> https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v7 commit 26 Feb
> >> 2021: 1151361fa7d45cc90d69086ccf1a4d8397931811 ) and the problem still
> >> exists.
> >>
> >> ** Affects: qemu
> >>       Importance: Undecided
> >>           Status: New
> >>
> >>
> >> ** Tags: riscv vector
> >>
> >> --
> >> You received this bug notification because you are a member of qemu-
> >> devel-ml, which is subscribed to QEMU.
> >> https://bugs.launchpad.net/bugs/1923629
> >>
> >> Title:
> >>    RISC-V Vector Instruction vssub.vv not saturating
> >>
> >> Status in QEMU:
> >>    New
> >>
> >> Bug description:
> >>    I noticed doing a negate ( 0 – 0x80000000 ) using vssub.vv produces an
> >>    incorrect result of 0x80000000 (should saturate to 0x7FFFFFFF).
> >>
> >>    Here is the bit of the code:
> >>
> >>                  vmv.v.i         v16, 0
> >>                  …
> >>    8f040457      vssub.vv        v8,v16,v8
> >>
> >>    I believe the instruction encoding is correct (vssub.vv with vd = v8,
> >>    vs2 = v16, rs1 = v8), but the result does not saturate in QEMU.
> >>
> >>    I’ve just tested with what I think is the latest branch (
> >>    https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v7 commit 26 Feb
> >>    2021: 1151361fa7d45cc90d69086ccf1a4d8397931811 ) and the problem still
> >>    exists.
> >>
> >> To manage notifications about this bug go to:
> >> https://bugs.launchpad.net/qemu/+bug/1923629/+subscriptions
> >>