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Re: [Bug 1923197] Re: RISC-V priviledged instruction error
From: |
Teodori Serge |
Subject: |
Re: [Bug 1923197] Re: RISC-V priviledged instruction error |
Date: |
Thu, 15 Apr 2021 06:05:02 -0000 |
Hello Francis,
I'll configure PMP than do the test again. Sorry I hadn't understood what
changed between version 5.2 and 6.0-rc2, since my code worked before.
Best regards,
Teodori Serge
On Thu, 15 Apr 2021, 06:15 Alistair Francis, <1923197@bugs.launchpad.net>
wrote:
> I'm guessing that this is a bug in your guest as it hasn't configured
> PMP regions.
>
> >From the RISC-V spec:
>
> "
> If no PMP entry matches an M-mode access, the access succeeds. If no PMP
> entry matches an
> S-mode or U-mode access, but at least one PMP entry is implemented, the
> access fails.
> "
>
> Confusingly implemented here means implemented in hardware, not just
> configured.
>
> ** Changed in: qemu
> Status: Confirmed => Invalid
>
> --
> You received this bug notification because you are subscribed to the bug
> report.
> https://bugs.launchpad.net/bugs/1923197
>
> Title:
> RISC-V priviledged instruction error
>
> To manage notifications about this bug go to:
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https://bugs.launchpad.net/bugs/1923197
Title:
RISC-V priviledged instruction error
Status in QEMU:
Invalid
Bug description:
Hello when performing an MRET with MPP set to something else than 0b11
in MSTATUS, 'Invalid Instruction' exception will be triggered. The
problem appeared in code after version 5.2.0. Use following code to
test.
# setup interrupt handling for monitor mode
la t0, entry_loop
la t1, entry_trap
li t2, 0x888
li t3, 0x1880
csrw mepc, t0
csrw mtvec, t1
csrs mie, t2
csrs mstatus, t3
# if supervisor mode not supported, then loop forever
csrr t0, misa
li t1, 0x40000
and t2, t1, t0
beqz t2, 1f
# setup interrupt i& exception delegation for supervisor mode
li t0, 0xc0000000 # 3 GiB (entry address of supervisor)
li t1, 0x1000
li t2, 0x300
li t3, 0x222
csrw mepc, t0
csrc mstatus, t1
csrs medeleg, t2
csrs mideleg, t3
# pass mhartid as first parameter to supervisor
csrr a0, mhartid
1:
mret
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