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Re: [EXTERNAL] [RFC PATCH 2/2] target/ppc: Add POWER10 exception model
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From: |
Cédric Le Goater |
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Subject: |
Re: [EXTERNAL] [RFC PATCH 2/2] target/ppc: Add POWER10 exception model |
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Date: |
Thu, 15 Apr 2021 08:50:57 +0200 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 |
On 4/15/21 7:28 AM, Nicholas Piggin wrote:
> Excerpts from Cédric Le Goater's message of April 15, 2021 1:54 am:
>> On 4/14/21 5:23 AM, Nicholas Piggin wrote:
>>> POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL],
>>> and it removes support for the LPCR[AIL]=0b10 mode.
>>
>> This looks good but it's missing the MSR_LE setting. A part from that :
>
> Oh, and lpes as well. Looks like a mis-merged from my original patch.
> Thanks for catching it, great.
>
>>
>> Reviewed-by: Cédric Le Goater <clg@kaod.org>
>>
>> and
>>
>> Tested-by: Cédric Le Goater <clg@kaod.org>
>
> Thanks, this was tested after you added the MSR_LE bit?
yes.
Thanks,
C.
>> distros using scv on P10 now need your patch to boot :
>>
>> "powerpc/powernv: Enable HAIL (HV AIL) for ISA v3.1 processors"
>>
>> I guess it will get merged in time.
>
> Yes, unfortunately. Real hardware crashes the same way though, so
> nothing to be done about it.