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[RFC v14 60/80] target/arm: cpu-sve: rename functions according to modul
From: |
Claudio Fontana |
Subject: |
[RFC v14 60/80] target/arm: cpu-sve: rename functions according to module prefix |
Date: |
Fri, 16 Apr 2021 18:28:04 +0200 |
external functions have the cpu_sve prefix,
while for static functions it can be omitted.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
target/arm/cpu-sve.h | 6 +++---
target/arm/cpu-sve.c | 32 ++++++++++++++++----------------
target/arm/cpu.c | 2 +-
target/arm/cpu64.c | 4 ++--
target/arm/kvm/kvm-cpu.c | 2 +-
5 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/target/arm/cpu-sve.h b/target/arm/cpu-sve.h
index 692509d419..ece36d2a0c 100644
--- a/target/arm/cpu-sve.h
+++ b/target/arm/cpu-sve.h
@@ -26,12 +26,12 @@
#include "cpu.h"
/* called by arm_cpu_finalize_features in realizefn */
-void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
+void cpu_sve_finalize_features(ARMCPU *cpu, Error **errp);
/* add the CPU SVE properties */
-void aarch64_add_sve_properties(Object *obj);
+void cpu_sve_add_props(Object *obj);
/* add the CPU SVE properties specific to the "MAX" CPU */
-void aarch64_add_sve_properties_max(Object *obj);
+void cpu_sve_add_props_max(Object *obj);
#endif /* CPU_SVE_H */
diff --git a/target/arm/cpu-sve.c b/target/arm/cpu-sve.c
index 129fb9586e..da60330cc2 100644
--- a/target/arm/cpu-sve.c
+++ b/target/arm/cpu-sve.c
@@ -27,7 +27,7 @@
#include "qapi/visitor.h"
#include "cpu-sve.h"
-void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
+void cpu_sve_finalize_features(ARMCPU *cpu, Error **errp)
{
/*
* If any vector lengths are explicitly enabled with sve<N> properties,
@@ -229,8 +229,8 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
cpu->sve_max_vq = max_vq;
}
-static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
+static void get_prop_max_vq(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
{
ARMCPU *cpu = ARM_CPU(obj);
uint32_t value;
@@ -244,8 +244,8 @@ static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v,
const char *name,
visit_type_uint32(v, name, &value, errp);
}
-static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
+static void set_prop_max_vq(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
{
ARMCPU *cpu = ARM_CPU(obj);
uint32_t max_vq;
@@ -276,8 +276,8 @@ static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v,
const char *name,
* of the contents of "name" to determine which bit on which
* to operate.
*/
-static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
+static void get_prop_vq(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
{
ARMCPU *cpu = ARM_CPU(obj);
uint32_t vq = atoi(&name[3]) / 128;
@@ -292,8 +292,8 @@ static void cpu_arm_get_sve_vq(Object *obj, Visitor *v,
const char *name,
visit_type_bool(v, name, &value, errp);
}
-static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
+static void set_prop_vq(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
{
ARMCPU *cpu = ARM_CPU(obj);
uint32_t vq = atoi(&name[3]) / 128;
@@ -317,13 +317,13 @@ static void cpu_arm_set_sve_vq(Object *obj, Visitor *v,
const char *name,
set_bit(vq - 1, cpu->sve_vq_init);
}
-static bool cpu_arm_get_sve(Object *obj, Error **errp)
+static bool get_prop_sve(Object *obj, Error **errp)
{
ARMCPU *cpu = ARM_CPU(obj);
return cpu_isar_feature(aa64_sve, cpu);
}
-static void cpu_arm_set_sve(Object *obj, bool value, Error **errp)
+static void set_prop_sve(Object *obj, bool value, Error **errp)
{
ARMCPU *cpu = ARM_CPU(obj);
uint64_t t;
@@ -338,21 +338,21 @@ static void cpu_arm_set_sve(Object *obj, bool value,
Error **errp)
cpu->isar.id_aa64pfr0 = t;
}
-void aarch64_add_sve_properties(Object *obj)
+void cpu_sve_add_props(Object *obj)
{
uint32_t vq;
- object_property_add_bool(obj, "sve", cpu_arm_get_sve, cpu_arm_set_sve);
+ object_property_add_bool(obj, "sve", get_prop_sve, set_prop_sve);
for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
char name[8];
sprintf(name, "sve%d", vq * 128);
- object_property_add(obj, name, "bool", cpu_arm_get_sve_vq,
cpu_arm_set_sve_vq, NULL, NULL);
+ object_property_add(obj, name, "bool", get_prop_vq, set_prop_vq, NULL,
NULL);
}
}
/* properties added for MAX CPU */
-void aarch64_add_sve_properties_max(Object *obj)
+void cpu_sve_add_props_max(Object *obj)
{
- object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_vq,
cpu_max_set_sve_max_vq, NULL, NULL);
+ object_property_add(obj, "sve-max-vq", "uint32", get_prop_max_vq,
set_prop_max_vq, NULL, NULL);
}
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 75a8041855..be5d857e65 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -821,7 +821,7 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)
#ifdef TARGET_AARCH64
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
- arm_cpu_sve_finalize(cpu, &local_err);
+ cpu_sve_finalize_features(cpu, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
return;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 52188698d9..7d6e0b553f 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -438,8 +438,8 @@ static void aarch64_max_initfn(Object *obj)
qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_property);
}
- aarch64_add_sve_properties(obj);
- aarch64_add_sve_properties_max(obj);
+ cpu_sve_add_props(obj);
+ cpu_sve_add_props_max(obj);
}
static const ARMCPUInfo aarch64_cpus[] = {
diff --git a/target/arm/kvm/kvm-cpu.c b/target/arm/kvm/kvm-cpu.c
index a23831e3c6..09aede9319 100644
--- a/target/arm/kvm/kvm-cpu.c
+++ b/target/arm/kvm/kvm-cpu.c
@@ -89,7 +89,7 @@ static void host_cpu_instance_init(Object *obj)
kvm_arm_set_cpu_features_from_host(cpu);
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
- aarch64_add_sve_properties(obj);
+ cpu_sve_add_props(obj);
}
arm_cpu_post_init(obj);
}
--
2.26.2
- [RFC v14 50/80] tests: restrict TCG-only arm-cpu-features tests to TCG builds, (continued)
- [RFC v14 50/80] tests: restrict TCG-only arm-cpu-features tests to TCG builds, Claudio Fontana, 2021/04/16
- [RFC v14 54/80] Revert "target/arm: Restrict v8M IDAU to TCG", Claudio Fontana, 2021/04/16
- [RFC v14 52/80] tests: device-introspect-test: cope with ARM TCG-only devices, Claudio Fontana, 2021/04/16
- [RFC v14 55/80] target/arm: create kvm cpu accel class, Claudio Fontana, 2021/04/16
- [RFC v14 51/80] tests: do not run test-hmp on all machines for ARM KVM-only, Claudio Fontana, 2021/04/16
- [RFC v14 57/80] target/arm: add tcg cpu accel class, Claudio Fontana, 2021/04/16
- [RFC v14 58/80] target/arm: move TCG gt timer creation code in tcg/, Claudio Fontana, 2021/04/16
- [RFC v14 64/80] target/arm: restrict rebuild_hflags_a64 to TARGET_AARCH64, Claudio Fontana, 2021/04/16
- [RFC v14 62/80] target/arm: cpu-sve: make cpu_sve_finalize_features return bool, Claudio Fontana, 2021/04/16
- [RFC v14 63/80] target/arm: make is_aa64 and arm_el_is_aa64 a macro for !TARGET_AARCH64, Claudio Fontana, 2021/04/16
- [RFC v14 60/80] target/arm: cpu-sve: rename functions according to module prefix,
Claudio Fontana <=
- [RFC v14 56/80] target/arm: move kvm post init initialization to kvm cpu accel, Claudio Fontana, 2021/04/16
- [RFC v14 61/80] target/arm: cpu-sve: split TCG and KVM functionality, Claudio Fontana, 2021/04/16
- [RFC v14 59/80] target/arm: cpu-sve: new module, Claudio Fontana, 2021/04/16
- [RFC v14 65/80] target/arm: arch_dump: restrict ELFCLASS64 to AArch64, Claudio Fontana, 2021/04/16
- [RFC v14 67/80] target/arm: tcg: restrict ZCR cpregs to TARGET_AARCH64, Claudio Fontana, 2021/04/16
- [RFC v14 71/80] cpu-sve: rename sve_zcr_len_for_el to cpu_sve_get_zcr_len_for_el, Claudio Fontana, 2021/04/16
- [RFC v14 66/80] target/arm: cpu-exceptions, cpu-exceptions-aa64: new modules, Claudio Fontana, 2021/04/16
- [RFC v14 72/80] target/arm: cpu-common: wrap a64-only check with is_a64, Claudio Fontana, 2021/04/16
- [RFC v14 70/80] target/arm: move sve_zcr_len_for_el to TARGET_AARCH64-only cpu-sve, Claudio Fontana, 2021/04/16
- [RFC v14 74/80] target/arm: cpu-pauth: change arm_cpu_pauth_finalize name and sig, Claudio Fontana, 2021/04/16