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[PATCH v4 14/30] target/arm: Enforce word alignment for LDRD/STRD
From: |
Richard Henderson |
Subject: |
[PATCH v4 14/30] target/arm: Enforce word alignment for LDRD/STRD |
Date: |
Fri, 16 Apr 2021 11:59:43 -0700 |
Buglink: https://bugs.launchpad.net/qemu/+bug/1905356
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 7472e98f09..63c665fb4e 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -6512,13 +6512,13 @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr
*a)
addr = op_addr_rr_pre(s, a);
tmp = tcg_temp_new_i32();
- gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
store_reg(s, a->rt, tmp);
tcg_gen_addi_i32(addr, addr, 4);
tmp = tcg_temp_new_i32();
- gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
store_reg(s, a->rt + 1, tmp);
/* LDRD w/ base writeback is undefined if the registers overlap. */
@@ -6541,13 +6541,13 @@ static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr
*a)
addr = op_addr_rr_pre(s, a);
tmp = load_reg(s, a->rt);
- gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
tcg_temp_free_i32(tmp);
tcg_gen_addi_i32(addr, addr, 4);
tmp = load_reg(s, a->rt + 1);
- gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
tcg_temp_free_i32(tmp);
op_addr_rr_post(s, a, addr, -4);
@@ -6649,13 +6649,13 @@ static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a,
int rt2)
addr = op_addr_ri_pre(s, a);
tmp = tcg_temp_new_i32();
- gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
store_reg(s, a->rt, tmp);
tcg_gen_addi_i32(addr, addr, 4);
tmp = tcg_temp_new_i32();
- gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
store_reg(s, rt2, tmp);
/* LDRD w/ base writeback is undefined if the registers overlap. */
@@ -6688,13 +6688,13 @@ static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a,
int rt2)
addr = op_addr_ri_pre(s, a);
tmp = load_reg(s, a->rt);
- gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
tcg_temp_free_i32(tmp);
tcg_gen_addi_i32(addr, addr, 4);
tmp = load_reg(s, rt2);
- gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
tcg_temp_free_i32(tmp);
op_addr_ri_post(s, a, addr, -4);
--
2.25.1
- [PATCH v4 10/30] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness, (continued)
- [PATCH v4 10/30] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness, Richard Henderson, 2021/04/16
- [PATCH v4 13/30] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness, Richard Henderson, 2021/04/16
- [PATCH v4 18/30] target/arm: Enforce alignment for SRS, Richard Henderson, 2021/04/16
- [PATCH v4 15/30] target/arm: Enforce alignment for LDA/LDAH/STL/STLH, Richard Henderson, 2021/04/16
- [PATCH v4 16/30] target/arm: Enforce alignment for LDM/STM, Richard Henderson, 2021/04/16
- [PATCH v4 19/30] target/arm: Enforce alignment for VLDM/VSTM, Richard Henderson, 2021/04/16
- [PATCH v4 20/30] target/arm: Enforce alignment for VLDR/VSTR, Richard Henderson, 2021/04/16
- [PATCH v4 21/30] target/arm: Enforce alignment for VLDn (all lanes), Richard Henderson, 2021/04/16
- [PATCH v4 22/30] target/arm: Enforce alignment for VLDn/VSTn (multiple), Richard Henderson, 2021/04/16
- [PATCH v4 17/30] target/arm: Enforce alignment for RFE, Richard Henderson, 2021/04/16
- [PATCH v4 14/30] target/arm: Enforce word alignment for LDRD/STRD,
Richard Henderson <=
- [PATCH v4 23/30] target/arm: Enforce alignment for VLDn/VSTn (single), Richard Henderson, 2021/04/16
- [PATCH v4 26/30] target/arm: Enforce alignment for aa64 load-acq/store-rel, Richard Henderson, 2021/04/16
- [PATCH v4 30/30] target/arm: Enforce alignment for sve LD1R, Richard Henderson, 2021/04/16
- [PATCH v4 24/30] target/arm: Use finalize_memop for aa64 gpr load/store, Richard Henderson, 2021/04/16
- [PATCH v4 25/30] target/arm: Use finalize_memop for aa64 fpr load/store, Richard Henderson, 2021/04/16
- [PATCH v4 28/30] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple), Richard Henderson, 2021/04/16
- [PATCH v4 29/30] target/arm: Enforce alignment for aa64 vector LDn/STn (single), Richard Henderson, 2021/04/16
- [PATCH v4 27/30] target/arm: Use MemOp for size + endian in aa64 vector ld/st, Richard Henderson, 2021/04/16
- Re: [PATCH v4 for-6.1 00/39] target/arm: enforce alignment, Peter Maydell, 2021/04/16