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Re: [PATCH v4 0/8] RISC-V: Add support for ePMP v0.9.1
From: |
Alistair Francis |
Subject: |
Re: [PATCH v4 0/8] RISC-V: Add support for ePMP v0.9.1 |
Date: |
Tue, 20 Apr 2021 09:13:59 +1000 |
On Mon, Apr 19, 2021 at 4:16 PM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> This series adds support for ePMP v0.9.1 to the QEMU RISC-V target.
>
> This is based on previous patches, but has been rebased on the latest
> master and updated for the latest spec.
>
> The spec is avaliable at:
> https://docs.google.com/document/d/1Mh_aiHYxemL0umN3GTTw8vsbmzHZ_nxZXgjgOUzbvc8
>
> This was tested by running Tock on the OpenTitan board.
>
> This is based on the original work by:
> Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
> Hou Weiying <weiying_hou@outlook.com>
> Myriad-Dreamin <camiyoru@gmail.com>
>
> v4:
> - Fix the pmpcfg write function and log
> v3:
> - Address Bin's comments on the ePMP implementation
> v2:
> - Rebase on the RISC-V tree
>
> Alistair Francis (4):
> target/riscv: Fix the PMP is locked check when using TOR
> target/riscv: Add the ePMP feature
> target/riscv/pmp: Remove outdated comment
> target/riscv: Add ePMP support for the Ibex CPU
>
> Hou Weiying (4):
> target/riscv: Define ePMP mseccfg
> target/riscv: Add ePMP CSR access functions
> target/riscv: Implementation of enhanced PMP (ePMP)
> target/riscv: Add a config option for ePMP
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> target/riscv/cpu.h | 3 +
> target/riscv/cpu_bits.h | 3 +
> target/riscv/pmp.h | 14 +++
> target/riscv/cpu.c | 11 ++
> target/riscv/csr.c | 24 +++++
> target/riscv/pmp.c | 218 ++++++++++++++++++++++++++++++++++----
> target/riscv/trace-events | 3 +
> 7 files changed, 254 insertions(+), 22 deletions(-)
>
> --
> 2.31.1
>
- [PATCH v4 0/8] RISC-V: Add support for ePMP v0.9.1, Alistair Francis, 2021/04/19
- [PATCH v4 1/8] target/riscv: Fix the PMP is locked check when using TOR, Alistair Francis, 2021/04/19
- [PATCH v4 2/8] target/riscv: Define ePMP mseccfg, Alistair Francis, 2021/04/19
- [PATCH v4 3/8] target/riscv: Add the ePMP feature, Alistair Francis, 2021/04/19
- [PATCH v4 4/8] target/riscv: Add ePMP CSR access functions, Alistair Francis, 2021/04/19
- [PATCH v4 5/8] target/riscv: Implementation of enhanced PMP (ePMP), Alistair Francis, 2021/04/19
- [PATCH v4 6/8] target/riscv: Add a config option for ePMP, Alistair Francis, 2021/04/19
- [PATCH v4 7/8] target/riscv/pmp: Remove outdated comment, Alistair Francis, 2021/04/19
- [PATCH v4 8/8] target/riscv: Add ePMP support for the Ibex CPU, Alistair Francis, 2021/04/19
- Re: [PATCH v4 0/8] RISC-V: Add support for ePMP v0.9.1,
Alistair Francis <=