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[PULL 00/43] target-arm queue
From: |
Peter Maydell |
Subject: |
[PULL 00/43] target-arm queue |
Date: |
Fri, 30 Apr 2021 11:33:54 +0100 |
First arm pullreq for 6.1 cycle. The big stuff here is RTH's alignment series.
thanks
-- PMM
The following changes since commit ccdf06c1db192152ac70a1dd974c624f566cb7d4:
Open 6.1 development tree (2021-04-30 11:15:40 +0100)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20210430
for you to fetch changes up to a6091108aa44e9017af4ca13c43f55a629e3744c:
hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows
(2021-04-30 11:16:52 +0100)
----------------------------------------------------------------
target-arm queue:
* hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows
* hw: add compat machines for 6.1
* Fault misaligned accesses where the architecture requires it
* Fix some corner cases of MTE faults (notably with misaligned accesses)
* Make Thumb store insns UNDEF for Rn==1111
* hw/arm/smmuv3: Support 16K translation granule
----------------------------------------------------------------
Cornelia Huck (1):
hw: add compat machines for 6.1
Kunkun Jiang (1):
hw/arm/smmuv3: Support 16K translation granule
Peter Maydell (2):
target/arm: Make Thumb store insns UNDEF for Rn==1111
hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows
Richard Henderson (39):
target/arm: Fix mte_checkN
target/arm: Split out mte_probe_int
target/arm: Fix unaligned checks for mte_check1, mte_probe1
test/tcg/aarch64: Add mte-5
target/arm: Replace MTEDESC ESIZE+TSIZE with SIZEM1
target/arm: Merge mte_check1, mte_checkN
target/arm: Rename mte_probe1 to mte_probe
target/arm: Simplify sve mte checking
target/arm: Remove log2_esize parameter to gen_mte_checkN
target/arm: Fix decode of align in VLDST_single
target/arm: Rename TBFLAG_A32, SCTLR_B
target/arm: Rename TBFLAG_ANY, PSTATE_SS
target/arm: Add wrapper macros for accessing tbflags
target/arm: Introduce CPUARMTBFlags
target/arm: Move mode specific TB flags to tb->cs_base
target/arm: Move TBFLAG_AM32 bits to the top
target/arm: Move TBFLAG_ANY bits to the bottom
target/arm: Add ALIGN_MEM to TBFLAG_ANY
target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness
target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64
target/arm: Fix SCTLR_B test for TCGv_i64 load/store
target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness
target/arm: Enforce word alignment for LDRD/STRD
target/arm: Enforce alignment for LDA/LDAH/STL/STLH
target/arm: Enforce alignment for LDM/STM
target/arm: Enforce alignment for RFE
target/arm: Enforce alignment for SRS
target/arm: Enforce alignment for VLDM/VSTM
target/arm: Enforce alignment for VLDR/VSTR
target/arm: Enforce alignment for VLDn (all lanes)
target/arm: Enforce alignment for VLDn/VSTn (multiple)
target/arm: Enforce alignment for VLDn/VSTn (single)
target/arm: Use finalize_memop for aa64 gpr load/store
target/arm: Use finalize_memop for aa64 fpr load/store
target/arm: Enforce alignment for aa64 load-acq/store-rel
target/arm: Use MemOp for size + endian in aa64 vector ld/st
target/arm: Enforce alignment for aa64 vector LDn/STn (multiple)
target/arm: Enforce alignment for aa64 vector LDn/STn (single)
target/arm: Enforce alignment for sve LD1R
include/hw/boards.h | 3 +
include/hw/i386/pc.h | 3 +
include/hw/pci-host/gpex.h | 4 +
target/arm/cpu.h | 105 ++++++++++-----
target/arm/helper-a64.h | 3 +-
target/arm/internals.h | 11 +-
target/arm/translate-a64.h | 2 +-
target/arm/translate.h | 38 ++++++
target/arm/neon-ls.decode | 4 +-
hw/arm/smmuv3.c | 6 +-
hw/arm/virt.c | 7 +-
hw/core/machine.c | 5 +
hw/i386/pc.c | 3 +
hw/i386/pc_piix.c | 14 +-
hw/i386/pc_q35.c | 13 +-
hw/pci-host/gpex.c | 56 +++++++-
hw/ppc/spapr.c | 17 ++-
hw/s390x/s390-virtio-ccw.c | 14 +-
target/arm/helper-a64.c | 2 +-
target/arm/helper.c | 162 ++++++++++++----------
target/arm/mte_helper.c | 185 ++++++++++---------------
target/arm/sve_helper.c | 100 +++++---------
target/arm/translate-a64.c | 236 ++++++++++++++++----------------
target/arm/translate-sve.c | 11 +-
target/arm/translate.c | 274 ++++++++++++++++++++++----------------
tests/tcg/aarch64/mte-5.c | 44 ++++++
target/arm/translate-neon.c.inc | 117 ++++++++++++----
target/arm/translate-vfp.c.inc | 20 +--
tests/tcg/aarch64/Makefile.target | 2 +-
29 files changed, 878 insertions(+), 583 deletions(-)
create mode 100644 tests/tcg/aarch64/mte-5.c
- [PULL 00/43] target-arm queue,
Peter Maydell <=
- [PULL 01/43] hw/arm/smmuv3: Support 16K translation granule, Peter Maydell, 2021/04/30
- [PULL 02/43] target/arm: Make Thumb store insns UNDEF for Rn==1111, Peter Maydell, 2021/04/30
- [PULL 03/43] target/arm: Fix mte_checkN, Peter Maydell, 2021/04/30
- [PULL 04/43] target/arm: Split out mte_probe_int, Peter Maydell, 2021/04/30
- [PULL 06/43] test/tcg/aarch64: Add mte-5, Peter Maydell, 2021/04/30
- [PULL 05/43] target/arm: Fix unaligned checks for mte_check1, mte_probe1, Peter Maydell, 2021/04/30
- [PULL 11/43] target/arm: Remove log2_esize parameter to gen_mte_checkN, Peter Maydell, 2021/04/30
- [PULL 07/43] target/arm: Replace MTEDESC ESIZE+TSIZE with SIZEM1, Peter Maydell, 2021/04/30
- [PULL 12/43] target/arm: Fix decode of align in VLDST_single, Peter Maydell, 2021/04/30
- [PULL 13/43] target/arm: Rename TBFLAG_A32, SCTLR_B, Peter Maydell, 2021/04/30