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[PULL 40/43] target/arm: Enforce alignment for aa64 vector LDn/STn (sing
From: |
Peter Maydell |
Subject: |
[PULL 40/43] target/arm: Enforce alignment for aa64 vector LDn/STn (single) |
Date: |
Fri, 30 Apr 2021 11:34:34 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-31-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-a64.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2a82dbbd6d4..95897e63af0 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -3815,6 +3815,7 @@ static void disas_ldst_single_struct(DisasContext *s,
uint32_t insn)
int index = is_q << 3 | S << 2 | size;
int xs, total;
TCGv_i64 clean_addr, tcg_rn, tcg_ebytes;
+ MemOp mop;
if (extract32(insn, 31, 1)) {
unallocated_encoding(s);
@@ -3876,6 +3877,7 @@ static void disas_ldst_single_struct(DisasContext *s,
uint32_t insn)
clean_addr = gen_mte_checkN(s, tcg_rn, !is_load, is_postidx || rn != 31,
total);
+ mop = finalize_memop(s, scale);
tcg_ebytes = tcg_const_i64(1 << scale);
for (xs = 0; xs < selem; xs++) {
@@ -3883,8 +3885,7 @@ static void disas_ldst_single_struct(DisasContext *s,
uint32_t insn)
/* Load and replicate to all elements */
TCGv_i64 tcg_tmp = tcg_temp_new_i64();
- tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr,
- get_mem_index(s), s->be_data + scale);
+ tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr, get_mem_index(s), mop);
tcg_gen_gvec_dup_i64(scale, vec_full_reg_offset(s, rt),
(is_q + 1) * 8, vec_full_reg_size(s),
tcg_tmp);
@@ -3892,9 +3893,9 @@ static void disas_ldst_single_struct(DisasContext *s,
uint32_t insn)
} else {
/* Load/store one element per register */
if (is_load) {
- do_vec_ld(s, rt, index, clean_addr, scale | s->be_data);
+ do_vec_ld(s, rt, index, clean_addr, mop);
} else {
- do_vec_st(s, rt, index, clean_addr, scale | s->be_data);
+ do_vec_st(s, rt, index, clean_addr, mop);
}
}
tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes);
--
2.20.1
- [PULL 25/43] target/arm: Enforce word alignment for LDRD/STRD, (continued)
- [PULL 25/43] target/arm: Enforce word alignment for LDRD/STRD, Peter Maydell, 2021/04/30
- [PULL 29/43] target/arm: Enforce alignment for SRS, Peter Maydell, 2021/04/30
- [PULL 16/43] target/arm: Introduce CPUARMTBFlags, Peter Maydell, 2021/04/30
- [PULL 24/43] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness, Peter Maydell, 2021/04/30
- [PULL 31/43] target/arm: Enforce alignment for VLDR/VSTR, Peter Maydell, 2021/04/30
- [PULL 28/43] target/arm: Enforce alignment for RFE, Peter Maydell, 2021/04/30
- [PULL 34/43] target/arm: Enforce alignment for VLDn/VSTn (single), Peter Maydell, 2021/04/30
- [PULL 39/43] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple), Peter Maydell, 2021/04/30
- [PULL 36/43] target/arm: Use finalize_memop for aa64 fpr load/store, Peter Maydell, 2021/04/30
- [PULL 35/43] target/arm: Use finalize_memop for aa64 gpr load/store, Peter Maydell, 2021/04/30
- [PULL 40/43] target/arm: Enforce alignment for aa64 vector LDn/STn (single),
Peter Maydell <=
- [PULL 43/43] hw/pci-host/gpex: Don't fault for unmapped parts of MMIO and PIO windows, Peter Maydell, 2021/04/30
- [PULL 41/43] target/arm: Enforce alignment for sve LD1R, Peter Maydell, 2021/04/30
- [PULL 30/43] target/arm: Enforce alignment for VLDM/VSTM, Peter Maydell, 2021/04/30
- [PULL 23/43] target/arm: Fix SCTLR_B test for TCGv_i64 load/store, Peter Maydell, 2021/04/30
- [PULL 33/43] target/arm: Enforce alignment for VLDn/VSTn (multiple), Peter Maydell, 2021/04/30
- [PULL 32/43] target/arm: Enforce alignment for VLDn (all lanes), Peter Maydell, 2021/04/30
- [PULL 37/43] target/arm: Enforce alignment for aa64 load-acq/store-rel, Peter Maydell, 2021/04/30
- [PULL 38/43] target/arm: Use MemOp for size + endian in aa64 vector ld/st, Peter Maydell, 2021/04/30
- [PULL 27/43] target/arm: Enforce alignment for LDM/STM, Peter Maydell, 2021/04/30
- [PULL 42/43] hw: add compat machines for 6.1, Peter Maydell, 2021/04/30