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[PULL 06/36] target/mips: Make check_cp0_enabled() return a boolean
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 06/36] target/mips: Make check_cp0_enabled() return a boolean |
Date: |
Sun, 2 May 2021 18:15:08 +0200 |
To avoid callers to emit dead code if check_cp0_enabled()
raise an exception, let it return a boolean value, whether
CP0 is enabled or not.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210420193453.1913810-4-f4bug@amsat.org>
---
target/mips/translate.h | 7 ++++++-
target/mips/translate.c | 4 +++-
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index 2b3c7a69ec6..61442590340 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -120,7 +120,12 @@ void gen_reserved_instruction(DisasContext *ctx);
void check_insn(DisasContext *ctx, uint64_t flags);
void check_mips_64(DisasContext *ctx);
-void check_cp0_enabled(DisasContext *ctx);
+/**
+ * check_cp0_enabled:
+ * Return %true if CP0 is enabled, otherwise return %false
+ * and emit a 'coprocessor unusable' exception.
+ */
+bool check_cp0_enabled(DisasContext *ctx);
void check_cp1_enabled(DisasContext *ctx);
void check_cp1_64bitmode(DisasContext *ctx);
void check_cp1_registers(DisasContext *ctx, int regs);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 3230b2bca3b..0e90d8cace6 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1572,11 +1572,13 @@ void gen_move_high32(TCGv ret, TCGv_i64 arg)
#endif
}
-void check_cp0_enabled(DisasContext *ctx)
+bool check_cp0_enabled(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) {
generate_exception_end(ctx, EXCP_CpU);
+ return false;
}
+ return true;
}
void check_cp1_enabled(DisasContext *ctx)
--
2.26.3
- [PULL 00/36] MIPS patches for 2021-05-02, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 01/36] hw/isa/piix4: Use qdev_get_gpio_in_named() to get ISA IRQ, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 02/36] target/mips: Fix CACHEE opcode (CACHE using EVA addressing), Philippe Mathieu-Daudé, 2021/05/02
- [PULL 03/36] target/mips: Add missing CP0 check to nanoMIPS RDPGPR / WRPGPR opcodes, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 04/36] target/mips: Remove spurious LOG_UNIMP of MTHC0 opcode, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 05/36] target/mips: Migrate missing CPU fields, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 06/36] target/mips: Make check_cp0_enabled() return a boolean,
Philippe Mathieu-Daudé <=
- [PULL 07/36] target/mips: Simplify meson TCG rules, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 08/36] target/mips: Move IEEE rounding mode array to new source file, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 09/36] target/mips: Move msa_reset() to new source file, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 10/36] target/mips: Make CPU/FPU regnames[] arrays global, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 11/36] target/mips: Optimize CPU/FPU regnames[] arrays, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 12/36] target/mips: Restrict mips_cpu_dump_state() to cpu.c, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 13/36] target/mips: Turn printfpr() macro into a proper function, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 14/36] target/mips: Declare mips_env_set_pc() inlined in "internal.h", Philippe Mathieu-Daudé, 2021/05/02
- [PULL 15/36] target/mips: Merge do_translate_address into cpu_mips_translate_address, Philippe Mathieu-Daudé, 2021/05/02
- [PULL 16/36] target/mips: Extract load/store helpers to ldst_helper.c, Philippe Mathieu-Daudé, 2021/05/02