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[PATCH 8/9] accel/tlb: Rename tlb_flush_[page_bits > range]_by_mmuidx_as
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH 8/9] accel/tlb: Rename tlb_flush_[page_bits > range]_by_mmuidx_async_[2 > 1] |
Date: |
Sun, 9 May 2021 17:16:17 +0200 |
From: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org>
[PMD: Split from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
accel/tcg/cputlb.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 47c83f0fc83..ad0e44bce63 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -816,8 +816,8 @@ static void tlb_flush_page_bits_by_mmuidx_async_1(CPUState
*cpu,
tlb_flush_range_by_mmuidx_async_0(cpu, decode_runon_to_pbm(runon));
}
-static void tlb_flush_page_bits_by_mmuidx_async_2(CPUState *cpu,
- run_on_cpu_data data)
+static void tlb_flush_range_by_mmuidx_async_1(CPUState *cpu,
+ run_on_cpu_data data)
{
TLBFlushRangeData *d = data.host_ptr;
tlb_flush_range_by_mmuidx_async_0(cpu, *d);
@@ -858,7 +858,7 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong
addr,
} else {
/* Otherwise allocate a structure, freed by the worker. */
TLBFlushRangeData *p = g_memdup(&d, sizeof(d));
- async_run_on_cpu(cpu, tlb_flush_page_bits_by_mmuidx_async_2,
+ async_run_on_cpu(cpu, tlb_flush_range_by_mmuidx_async_1,
RUN_ON_CPU_HOST_PTR(p));
}
}
@@ -906,7 +906,7 @@ void tlb_flush_range_by_mmuidx_all_cpus(CPUState *src_cpu,
if (dst_cpu != src_cpu) {
TLBFlushRangeData *p = g_memdup(&d, sizeof(d));
async_run_on_cpu(dst_cpu,
- tlb_flush_page_bits_by_mmuidx_async_2,
+ tlb_flush_range_by_mmuidx_async_1,
RUN_ON_CPU_HOST_PTR(p));
}
}
@@ -964,13 +964,13 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState
*src_cpu,
CPU_FOREACH(dst_cpu) {
if (dst_cpu != src_cpu) {
p = g_memdup(&d, sizeof(d));
- async_run_on_cpu(dst_cpu,
tlb_flush_page_bits_by_mmuidx_async_2,
+ async_run_on_cpu(dst_cpu, tlb_flush_range_by_mmuidx_async_1,
RUN_ON_CPU_HOST_PTR(p));
}
}
p = g_memdup(&d, sizeof(d));
- async_safe_run_on_cpu(src_cpu, tlb_flush_page_bits_by_mmuidx_async_2,
+ async_safe_run_on_cpu(src_cpu, tlb_flush_range_by_mmuidx_async_1,
RUN_ON_CPU_HOST_PTR(p));
}
}
--
2.26.3
- [PATCH 3/9] accel/tlb: Rename TLBFlushPageBitsByMMUIdxData -> TLBFlushRangeData, (continued)
- [PATCH 3/9] accel/tlb: Rename TLBFlushPageBitsByMMUIdxData -> TLBFlushRangeData, Philippe Mathieu-Daudé, 2021/05/09
- [PATCH 4/9] accel/tcg: Add tlb_flush_range_by_mmuidx(), Philippe Mathieu-Daudé, 2021/05/09
- [PATCH 5/9] accel/tcg: Add tlb_flush_page_bits_by_mmuidx_all_cpus(), Philippe Mathieu-Daudé, 2021/05/09
- [PATCH 6/9] accel/tlb: Add tlb_flush_range_by_mmuidx_all_cpus_synced(), Philippe Mathieu-Daudé, 2021/05/09
- [PATCH 7/9] accel/tcg: Rename tlb_flush_page_bits -> range]_by_mmuidx_async_0, Philippe Mathieu-Daudé, 2021/05/09
- [PATCH 8/9] accel/tlb: Rename tlb_flush_[page_bits > range]_by_mmuidx_async_[2 > 1],
Philippe Mathieu-Daudé <=
- [PATCH 9/9] accel/tcg: Remove tlb_flush_page_bits_by_mmuidx_async_1() ???, Philippe Mathieu-Daudé, 2021/05/09
- Re: [PATCH 0/9] accel/tcg: Add tlb_flush interface for a range of pages, Philippe Mathieu-Daudé, 2021/05/09
- Re: [PATCH 0/9] accel/tcg: Add tlb_flush interface for a range of pages, Peter Maydell, 2021/05/25