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Re: [PULL v2 00/42] riscv-to-apply queue
From: |
Alistair Francis |
Subject: |
Re: [PULL v2 00/42] riscv-to-apply queue |
Date: |
Tue, 11 May 2021 20:17:24 +1000 |
On Tue, May 11, 2021 at 6:30 PM Peter Maydell <peter.maydell@linaro.org> wrote:
>
> On Thu, 6 May 2021 at 00:23, Alistair Francis <alistair.francis@wdc.com>
> wrote:
> >
> > The following changes since commit d45a5270d075ea589f0b0ddcf963a5fea1f500ac:
> >
> > Merge remote-tracking branch
> > 'remotes/vivier2/tags/trivial-branch-for-6.1-pull-request' into staging
> > (2021-05-05 13:52:00 +0100)
> >
> > are available in the Git repository at:
> >
> > git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210506
> >
> > for you to fetch changes up to d9e1a4683bc52ff218dcc133f73017bc4c496346:
> >
> > target/riscv: Fix the RV64H decode comment (2021-05-06 08:59:59 +1000)
> >
> > ----------------------------------------------------------------
> > A large collection of RISC-V fixes, improvements and features
> >
> > - Clenaup some left over v1.9 code
> > - Documentation improvements
> > - Support for the shakti_c machine
> > - Internal cleanup of the CSR accesses
> > - Updates to the OpenTitan platform
> > - Support for the virtio-vga
> > - Fix for the saturate subtract in vector extensions
> > - Experimental support for the ePMP spec
> > - A range of other internal code cleanups and bug fixes
> >
>
> This triggers new runtime errors in the clang sanitizer build:
>
> MALLOC_PERTURB_=${MALLOC_PERTURB_:-$(( ${RANDOM:-0} % 255 + 1))}
> QTEST_QEMU_IMG=./qemu-img
> G_TEST_DBUS_DAEMON=/home/petmay01/linaro/qemu-for-merges/tests/dbus-
> vmstate-daemon.sh QTEST_QEMU_BINARY=./qemu-system-riscv64
> tests/qtest/qom-test --tap -k
> PASS 1 qtest-riscv64/qom-test /riscv64/qom/virt
> PASS 2 qtest-riscv64/qom-test /riscv64/qom/none
> PASS 3 qtest-riscv64/qom-test /riscv64/qom/microchip-icicle-kit
> PASS 4 qtest-riscv64/qom-test /riscv64/qom/spike
> PASS 5 qtest-riscv64/qom-test /riscv64/qom/sifive_e
> ../../hw/core/loader.c:459:15: runtime error: null pointer passed as
> argument 1, which is declared to never be null
> /usr/include/fcntl.h:161:6: note: nonnull attribute specified here
> Bad address
> ../../hw/core/loader.c:73:15: runtime error: null pointer passed as
> argument 1, which is declared to never be null
> /usr/include/fcntl.h:161:6: note: nonnull attribute specified here
> PASS 6 qtest-riscv64/qom-test /riscv64/qom/shakti_c
> PASS 7 qtest-riscv64/qom-test /riscv64/qom/sifive_u
>
> (and same again in the test-hmp test)
>
> Looks like something's passing a NULL filename to an image
> loading function.
Strange. I can easily reproduce this failure but `make check` still
returns 0. So although my tests saw the error they never failed and
because of that I never noticed the problem (I only read the logs on
failures).
It seems this is from the shakti_c machine, I have fixed it and will
send a new PR.
Alistair
>
> thanks
> -- PMM
- [PULL v2 34/42] target/riscv: Remove the hardcoded SSTATUS_SD macro, (continued)
- [PULL v2 34/42] target/riscv: Remove the hardcoded SSTATUS_SD macro, Alistair Francis, 2021/05/05
- [PULL v2 35/42] target/riscv: Remove the hardcoded HGATP_MODE macro, Alistair Francis, 2021/05/05
- [PULL v2 36/42] target/riscv: Remove the hardcoded MSTATUS_SD macro, Alistair Francis, 2021/05/05
- [PULL v2 38/42] target/riscv: Remove the unused HSTATUS_WPRI macro, Alistair Francis, 2021/05/05
- [PULL v2 37/42] target/riscv: Remove the hardcoded SATP_MODE macro, Alistair Francis, 2021/05/05
- [PULL v2 39/42] target/riscv: Remove an unused CASE_OP_32_64 macro, Alistair Francis, 2021/05/05
- [PULL v2 40/42] target/riscv: Consolidate RV32/64 32-bit instructions, Alistair Francis, 2021/05/05
- [PULL v2 41/42] target/riscv: Consolidate RV32/64 16-bit instructions, Alistair Francis, 2021/05/05
- [PULL v2 42/42] target/riscv: Fix the RV64H decode comment, Alistair Francis, 2021/05/05
- Re: [PULL v2 00/42] riscv-to-apply queue, Peter Maydell, 2021/05/11
- Re: [PULL v2 00/42] riscv-to-apply queue,
Alistair Francis <=