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[PULL v3 33/42] target/riscv: Remove the hardcoded RVXLEN macro
From: |
Alistair Francis |
Subject: |
[PULL v3 33/42] target/riscv: Remove the hardcoded RVXLEN macro |
Date: |
Tue, 11 May 2021 20:19:42 +1000 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
a07bc0c6dc4958681b4f93cbc5d0acc31ed3344a.1619234854.git.alistair.francis@wdc.com
---
target/riscv/cpu.h | 6 ------
target/riscv/cpu.c | 6 +++++-
2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index add734bbbd..7e879fb9ca 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -54,12 +54,6 @@
#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
-#if defined(TARGET_RISCV32)
-#define RVXLEN RV32
-#elif defined(TARGET_RISCV64)
-#define RVXLEN RV64
-#endif
-
#define RV(x) ((target_ulong)1 << (x - 'A'))
#define RVI RV('I')
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 04ac03f8c9..3191fd0082 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -147,7 +147,11 @@ static void set_resetvec(CPURISCVState *env, target_ulong
resetvec)
static void riscv_any_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
- set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+#if defined(TARGET_RISCV32)
+ set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+#elif defined(TARGET_RISCV64)
+ set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
+#endif
set_priv_version(env, PRIV_VERSION_1_11_0);
}
--
2.31.1
- Re: [PULL v3 24/42] target/riscv: Implementation of enhanced PMP (ePMP), (continued)
- [PULL v3 25/42] target/riscv: Add a config option for ePMP, Alistair Francis, 2021/05/11
- [PULL v3 28/42] target/riscv: fix vrgather macro index variable type bug, Alistair Francis, 2021/05/11
- [PULL v3 27/42] target/riscv: Add ePMP support for the Ibex CPU, Alistair Francis, 2021/05/11
- [PULL v3 26/42] target/riscv/pmp: Remove outdated comment, Alistair Francis, 2021/05/11
- [PULL v3 30/42] hw/riscv: Fix OT IBEX reset vector, Alistair Francis, 2021/05/11
- [PULL v3 31/42] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions, Alistair Francis, 2021/05/11
- [PULL v3 29/42] target/riscv: fix exception index on instruction access fault, Alistair Francis, 2021/05/11
- [PULL v3 32/42] target/riscv: fix a typo with interrupt names, Alistair Francis, 2021/05/11
- [PULL v3 34/42] target/riscv: Remove the hardcoded SSTATUS_SD macro, Alistair Francis, 2021/05/11
- [PULL v3 33/42] target/riscv: Remove the hardcoded RVXLEN macro,
Alistair Francis <=
- [PULL v3 35/42] target/riscv: Remove the hardcoded HGATP_MODE macro, Alistair Francis, 2021/05/11
- [PULL v3 36/42] target/riscv: Remove the hardcoded MSTATUS_SD macro, Alistair Francis, 2021/05/11
[PULL v3 37/42] target/riscv: Remove the hardcoded SATP_MODE macro, Alistair Francis, 2021/05/11
[PULL v3 38/42] target/riscv: Remove the unused HSTATUS_WPRI macro, Alistair Francis, 2021/05/11
[PULL v3 39/42] target/riscv: Remove an unused CASE_OP_32_64 macro, Alistair Francis, 2021/05/11
[PULL v3 40/42] target/riscv: Consolidate RV32/64 32-bit instructions, Alistair Francis, 2021/05/11