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Re: [PATCH 03/11] target/ppc: moved ppc_cpu_dump_state to cpu_init.c
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From: |
David Gibson |
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Subject: |
Re: [PATCH 03/11] target/ppc: moved ppc_cpu_dump_state to cpu_init.c |
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Date: |
Thu, 13 May 2021 13:51:55 +1000 |
On Wed, May 12, 2021 at 11:08:05AM -0300, Bruno Larsen (billionai) wrote:
> This function was forgotten in the cpu_init code motion series, but it
> seems to be used regardless of TCG, and so needs to be moved to support
> disabling TCG.
>
> Signed-off-by: Bruno Larsen (billionai)
> <bruno.larsen@eldorado.org.br>
Applied to ppc-for-6.1, thanks.
> ---
> target/ppc/cpu_init.c | 182 +++++++++++++++++++++++++++++++++++++++
> target/ppc/translate.c | 187 -----------------------------------------
> 2 files changed, 182 insertions(+), 187 deletions(-)
>
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index b4a2d15c6a..d0fa219880 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -9366,4 +9366,186 @@ static void ppc_cpu_register_types(void)
> #endif
> }
>
> +void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
> +{
> +#define RGPL 4
> +#define RFPL 4
> +
> + PowerPCCPU *cpu = POWERPC_CPU(cs);
> + CPUPPCState *env = &cpu->env;
> + int i;
> +
> + qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
> + TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
> + env->nip, env->lr, env->ctr, cpu_read_xer(env),
> + cs->cpu_index);
> + qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
> + "%08x iidx %d didx %d\n",
> + env->msr, env->spr[SPR_HID0], env->hflags,
> + cpu_mmu_index(env, true), cpu_mmu_index(env, false));
> +#if !defined(NO_TIMER_DUMP)
> + qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
> +#if !defined(CONFIG_USER_ONLY)
> + " DECR " TARGET_FMT_lu
> +#endif
> + "\n",
> + cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
> +#if !defined(CONFIG_USER_ONLY)
> + , cpu_ppc_load_decr(env)
> +#endif
> + );
> +#endif
> + for (i = 0; i < 32; i++) {
> + if ((i & (RGPL - 1)) == 0) {
> + qemu_fprintf(f, "GPR%02d", i);
> + }
> + qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
> + if ((i & (RGPL - 1)) == (RGPL - 1)) {
> + qemu_fprintf(f, "\n");
> + }
> + }
> + qemu_fprintf(f, "CR ");
> + for (i = 0; i < 8; i++)
> + qemu_fprintf(f, "%01x", env->crf[i]);
> + qemu_fprintf(f, " [");
> + for (i = 0; i < 8; i++) {
> + char a = '-';
> + if (env->crf[i] & 0x08) {
> + a = 'L';
> + } else if (env->crf[i] & 0x04) {
> + a = 'G';
> + } else if (env->crf[i] & 0x02) {
> + a = 'E';
> + }
> + qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
> + }
> + qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
> + env->reserve_addr);
> +
> + if (flags & CPU_DUMP_FPU) {
> + for (i = 0; i < 32; i++) {
> + if ((i & (RFPL - 1)) == 0) {
> + qemu_fprintf(f, "FPR%02d", i);
> + }
> + qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i));
> + if ((i & (RFPL - 1)) == (RFPL - 1)) {
> + qemu_fprintf(f, "\n");
> + }
> + }
> + qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
> + }
> +
> +#if !defined(CONFIG_USER_ONLY)
> + qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
> + " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
> + env->spr[SPR_SRR0], env->spr[SPR_SRR1],
> + env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
> +
> + qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
> + " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
> + env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
> + env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
> +
> + qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
> + " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
> + env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
> + env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
> +
> +#if defined(TARGET_PPC64)
> + if (env->excp_model == POWERPC_EXCP_POWER7 ||
> + env->excp_model == POWERPC_EXCP_POWER8 ||
> + env->excp_model == POWERPC_EXCP_POWER9 ||
> + env->excp_model == POWERPC_EXCP_POWER10) {
> + qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
> + env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
> + }
> +#endif
> + if (env->excp_model == POWERPC_EXCP_BOOKE) {
> + qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
> + " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
> + env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
> + env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
> +
> + qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
> + " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
> + env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
> + env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
> +
> + qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
> + " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
> + env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
> + env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
> +
> + qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
> + " EPR " TARGET_FMT_lx "\n",
> + env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
> + env->spr[SPR_BOOKE_EPR]);
> +
> + /* FSL-specific */
> + qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
> + " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
> + env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
> + env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
> +
> + /*
> + * IVORs are left out as they are large and do not change often --
> + * they can be read with "p $ivor0", "p $ivor1", etc.
> + */
> + }
> +
> +#if defined(TARGET_PPC64)
> + if (env->flags & POWERPC_FLAG_CFAR) {
> + qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
> + }
> +#endif
> +
> + if (env->spr_cb[SPR_LPCR].name) {
> + qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
> + }
> +
> + switch (env->mmu_model) {
> + case POWERPC_MMU_32B:
> + case POWERPC_MMU_601:
> + case POWERPC_MMU_SOFT_6xx:
> + case POWERPC_MMU_SOFT_74xx:
> +#if defined(TARGET_PPC64)
> + case POWERPC_MMU_64B:
> + case POWERPC_MMU_2_03:
> + case POWERPC_MMU_2_06:
> + case POWERPC_MMU_2_07:
> + case POWERPC_MMU_3_00:
> +#endif
> + if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
> + qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
> + }
> + if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
> + qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
> + }
> + qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
> + env->spr[SPR_DAR], env->spr[SPR_DSISR]);
> + break;
> + case POWERPC_MMU_BOOKE206:
> + qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
> + " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
> + env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
> + env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
> +
> + qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
> + " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
> + env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
> + env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
> +
> + qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
> + " TLB1CFG " TARGET_FMT_lx "\n",
> + env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
> + env->spr[SPR_BOOKE_TLB1CFG]);
> + break;
> + default:
> + break;
> + }
> +#endif
> +
> +#undef RGPL
> +#undef RFPL
> +}
> type_init(ppc_cpu_register_types)
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 5e3495e018..6c68d7006a 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -8617,193 +8617,6 @@ GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E,
> 0x1F, 0x03FFF800, \
> #include "translate/spe-ops.c.inc"
> };
>
> -#include "helper_regs.h"
> -
> -/*****************************************************************************/
> -/* Misc PowerPC helpers */
> -void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
> -{
> -#define RGPL 4
> -#define RFPL 4
> -
> - PowerPCCPU *cpu = POWERPC_CPU(cs);
> - CPUPPCState *env = &cpu->env;
> - int i;
> -
> - qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
> - TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n",
> - env->nip, env->lr, env->ctr, cpu_read_xer(env),
> - cs->cpu_index);
> - qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
> - "%08x iidx %d didx %d\n",
> - env->msr, env->spr[SPR_HID0], env->hflags,
> - cpu_mmu_index(env, true), cpu_mmu_index(env, false));
> -#if !defined(NO_TIMER_DUMP)
> - qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
> -#if !defined(CONFIG_USER_ONLY)
> - " DECR " TARGET_FMT_lu
> -#endif
> - "\n",
> - cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
> -#if !defined(CONFIG_USER_ONLY)
> - , cpu_ppc_load_decr(env)
> -#endif
> - );
> -#endif
> - for (i = 0; i < 32; i++) {
> - if ((i & (RGPL - 1)) == 0) {
> - qemu_fprintf(f, "GPR%02d", i);
> - }
> - qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
> - if ((i & (RGPL - 1)) == (RGPL - 1)) {
> - qemu_fprintf(f, "\n");
> - }
> - }
> - qemu_fprintf(f, "CR ");
> - for (i = 0; i < 8; i++)
> - qemu_fprintf(f, "%01x", env->crf[i]);
> - qemu_fprintf(f, " [");
> - for (i = 0; i < 8; i++) {
> - char a = '-';
> - if (env->crf[i] & 0x08) {
> - a = 'L';
> - } else if (env->crf[i] & 0x04) {
> - a = 'G';
> - } else if (env->crf[i] & 0x02) {
> - a = 'E';
> - }
> - qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
> - }
> - qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
> - env->reserve_addr);
> -
> - if (flags & CPU_DUMP_FPU) {
> - for (i = 0; i < 32; i++) {
> - if ((i & (RFPL - 1)) == 0) {
> - qemu_fprintf(f, "FPR%02d", i);
> - }
> - qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i));
> - if ((i & (RFPL - 1)) == (RFPL - 1)) {
> - qemu_fprintf(f, "\n");
> - }
> - }
> - qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
> - }
> -
> -#if !defined(CONFIG_USER_ONLY)
> - qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
> - " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
> - env->spr[SPR_SRR0], env->spr[SPR_SRR1],
> - env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
> -
> - qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
> - " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
> - env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
> - env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
> -
> - qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
> - " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
> - env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
> - env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
> -
> -#if defined(TARGET_PPC64)
> - if (env->excp_model == POWERPC_EXCP_POWER7 ||
> - env->excp_model == POWERPC_EXCP_POWER8 ||
> - env->excp_model == POWERPC_EXCP_POWER9 ||
> - env->excp_model == POWERPC_EXCP_POWER10) {
> - qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n",
> - env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]);
> - }
> -#endif
> - if (env->excp_model == POWERPC_EXCP_BOOKE) {
> - qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
> - " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
> - env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
> - env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
> -
> - qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
> - " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
> - env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
> - env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
> -
> - qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
> - " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
> - env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
> - env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
> -
> - qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
> - " EPR " TARGET_FMT_lx "\n",
> - env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
> - env->spr[SPR_BOOKE_EPR]);
> -
> - /* FSL-specific */
> - qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
> - " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
> - env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
> - env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
> -
> - /*
> - * IVORs are left out as they are large and do not change often --
> - * they can be read with "p $ivor0", "p $ivor1", etc.
> - */
> - }
> -
> -#if defined(TARGET_PPC64)
> - if (env->flags & POWERPC_FLAG_CFAR) {
> - qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
> - }
> -#endif
> -
> - if (env->spr_cb[SPR_LPCR].name) {
> - qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]);
> - }
> -
> - switch (env->mmu_model) {
> - case POWERPC_MMU_32B:
> - case POWERPC_MMU_601:
> - case POWERPC_MMU_SOFT_6xx:
> - case POWERPC_MMU_SOFT_74xx:
> -#if defined(TARGET_PPC64)
> - case POWERPC_MMU_64B:
> - case POWERPC_MMU_2_03:
> - case POWERPC_MMU_2_06:
> - case POWERPC_MMU_2_07:
> - case POWERPC_MMU_3_00:
> -#endif
> - if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */
> - qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
> - }
> - if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */
> - qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]);
> - }
> - qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n",
> - env->spr[SPR_DAR], env->spr[SPR_DSISR]);
> - break;
> - case POWERPC_MMU_BOOKE206:
> - qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
> - " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
> - env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
> - env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
> -
> - qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
> - " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
> - env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
> - env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
> -
> - qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
> - " TLB1CFG " TARGET_FMT_lx "\n",
> - env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
> - env->spr[SPR_BOOKE_TLB1CFG]);
> - break;
> - default:
> - break;
> - }
> -#endif
> -
> -#undef RGPL
> -#undef RFPL
> -}
> -
>
> /*****************************************************************************/
> /* Opcode types */
> enum {
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [RFC PATCH 00/11] target/ppc: add support to disable-tcg, Bruno Larsen (billionai), 2021/05/12
- [PATCH 01/11] target/ppc: created ppc_{store, get}_vscr for generic vscr usage, Bruno Larsen (billionai), 2021/05/12
- [PATCH 02/11] target/ppc: moved ppc_store_sdr1 to cpu.c, Bruno Larsen (billionai), 2021/05/12
- [PATCH 03/11] target/ppc: moved ppc_cpu_dump_state to cpu_init.c, Bruno Larsen (billionai), 2021/05/12
- [PATCH 04/11] target/ppc: moved ppc_store_msr into gdbstub.c, Bruno Larsen (billionai), 2021/05/12
- [PATCH 05/11] target/ppc: moved ppc_store_lpcr to cpu.c, Bruno Larsen (billionai), 2021/05/12
- [PATCH 06/11] target/ppc: updated vscr manipulation in machine.c, Bruno Larsen (billionai), 2021/05/12
- [PATCH 07/11] target/ppc: added KVM fallback to fpscr manipulation, Bruno Larsen (billionai), 2021/05/12