Re: [PATCH v6 72/82] target/arm: Implement SVE2 bitwise shift immediate

[Peter Maydell]

On Fri, 30 Apr 2021 at 22:17, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> From: Stephen Long <steplong@quicinc.com>
>
> Implements SQSHL/UQSHL, SRSHR/URSHR, and SQSHLU
>
> Signed-off-by: Stephen Long <steplong@quicinc.com>
> Message-Id: <20200430194159.24064-1-steplong@quicinc.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/helper-sve.h    | 33 +++++++++++++++++++++
>  target/arm/sve.decode      |  5 ++++
>  target/arm/sve_helper.c    | 35 ++++++++++++++++++++++
>  target/arm/translate-sve.c | 60 ++++++++++++++++++++++++++++++++++++++
>  4 files changed, 133 insertions(+)
>


> +/* SVE2 bitwise shift by immediate */
> +DO_ZPZI(sve2_sqshl_zpzi_b, int8_t, H1, do_sqshl_b)
> +DO_ZPZI(sve2_sqshl_zpzi_h, int16_t, H1_2, do_sqshl_h)
> +DO_ZPZI(sve2_sqshl_zpzi_s, int32_t, H1_4, do_sqshl_s)
> +DO_ZPZI_D(sve2_sqshl_zpzi_d, int64_t, do_sqshl_d)

What is the rule for when a set of operations on (8, 16, 32, 64) bit
values should use (H1, H2, H4, ""), and when it should
use (H1, H1_2, H1_4, "") ?

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM