[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 1/4] target/riscv: Add defines for AIA local interrupt CSRs
|
From: |
Anup Patel |
|
Subject: |
[PATCH 1/4] target/riscv: Add defines for AIA local interrupt CSRs |
|
Date: |
Fri, 14 May 2021 20:02:39 +0530 |
The RISC-V AIA specification extends RISC-V local interrupts and
introduces new CSRs. This patch adds defines for the new AIA
local interrupt CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
target/riscv/cpu_bits.h | 128 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 128 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index caf4599207..d23242655e 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -169,6 +169,31 @@
/* Legacy Machine Trap Handling (priv v1.9.1) */
#define CSR_MBADADDR 0x343
+/* Machine-Level Window to Indirectly Accessed Registers (AIA) */
+#define CSR_MISELECT 0x350
+#define CSR_MIREG 0x351
+
+/* Machine-Level Interrupts (AIA) */
+#define CSR_MTOPI 0xfb0
+
+/* Machine-Level IMSIC Interface (AIA) */
+#define CSR_MSETEIPNUM 0x358
+#define CSR_MCLREIPNUM 0x359
+#define CSR_MSETEIENUM 0x35a
+#define CSR_MCLREIENUM 0x35b
+#define CSR_MCLAIMEI 0xfa8
+
+/* Virtual Interrupts for Supervisor Level (AIA) */
+#define CSR_MVIEN 0x308
+#define CSR_MVIP 0x309
+
+/* Machine-Level High-Half CSRs (AIA) */
+#define CSR_MIDELEGH 0x313
+#define CSR_MIEH 0x314
+#define CSR_MVIENH 0x318
+#define CSR_MVIPH 0x319
+#define CSR_MIPH 0x354
+
/* Supervisor Trap Setup */
#define CSR_SSTATUS 0x100
#define CSR_SEDELEG 0x102
@@ -191,6 +216,24 @@
#define CSR_SPTBR 0x180
#define CSR_SATP 0x180
+/* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
+#define CSR_SISELECT 0x150
+#define CSR_SIREG 0x151
+
+/* Supervisor-Level Interrupts (AIA) */
+#define CSR_STOPI 0xdb0
+
+/* Supervisor-Level IMSIC Interface (AIA) */
+#define CSR_SSETEIPNUM 0x158
+#define CSR_SCLREIPNUM 0x159
+#define CSR_SSETEIENUM 0x15a
+#define CSR_SCLREIENUM 0x15b
+#define CSR_SCLAIMEI 0xda8
+
+/* Supervisor-Level High-Half CSRs (AIA) */
+#define CSR_SIEH 0x114
+#define CSR_SIPH 0x154
+
/* Hpervisor CSRs */
#define CSR_HSTATUS 0x600
#define CSR_HEDELEG 0x602
@@ -232,6 +275,34 @@
#define CSR_MTINST 0x34a
#define CSR_MTVAL2 0x34b
+/* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
+#define CSR_HVIEN 0x608
+#define CSR_HVICONTROL 0x609
+#define CSR_HVIPRIO1 0x646
+#define CSR_HVIPRIO2 0x647
+
+/* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */
+#define CSR_VSISELECT 0x250
+#define CSR_VSIREG 0x251
+
+/* VS-Level Interrupts (H-extension with AIA) */
+#define CSR_VSTOPI 0xeb0
+
+/* VS-Level IMSIC Interface (H-extension with AIA) */
+#define CSR_VSSETEIPNUM 0x258
+#define CSR_VSCLREIPNUM 0x259
+#define CSR_VSSETEIENUM 0x25a
+#define CSR_VSCLREIENUM 0x25b
+
+/* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
+#define CSR_HIDELEGH 0x613
+#define CSR_HVIENH 0x618
+#define CSR_HVIPH 0x655
+#define CSR_HVIPRIO1H 0x656
+#define CSR_HVIPRIO2H 0x657
+#define CSR_VSIEH 0x214
+#define CSR_VSIPH 0x254
+
/* Physical Memory Protection */
#define CSR_PMPCFG0 0x3a0
#define CSR_PMPCFG1 0x3a1
@@ -436,6 +507,7 @@
#define HSTATUS_SPVP 0x00000100
#define HSTATUS_HU 0x00000200
#define HSTATUS_VGEIN 0x0003F000
+#define HSTATUS_VGEIN_SHIFT 12
#define HSTATUS_VTVM 0x00100000
#define HSTATUS_VTSR 0x00400000
#define HSTATUS_VSXL 0x300000000
@@ -565,6 +637,7 @@
#define IRQ_S_EXT 9
#define IRQ_VS_EXT 10
#define IRQ_M_EXT 11
+#define IRQ_S_GEXT 12
/* mip masks */
#define MIP_USIP (1 << IRQ_U_SOFT)
@@ -592,4 +665,59 @@
#define MIE_UTIE (1 << IRQ_U_TIMER)
#define MIE_SSIE (1 << IRQ_S_SOFT)
#define MIE_USIE (1 << IRQ_U_SOFT)
+
+/* MISELECT, SISELECT, and VSISELECT bits (AIA) */
+#define ISELECT_IPRIO0 0x30
+#define ISELECT_IPRIO15 0x3f
+#define ISELECT_IMSIC_EIDELIVERY 0x70
+#define ISELECT_IMSIC_EITHRESHOLD 0x72
+#define ISELECT_IMSIC_TOPEI 0x76
+#define ISELECT_IMSIC_EIP0 0x80
+#define ISELECT_IMSIC_EIP63 0xbf
+#define ISELECT_IMSIC_EIE0 0xc0
+#define ISELECT_IMSIC_EIE63 0xff
+#define ISELECT_IMSIC_FIRST ISELECT_IMSIC_EIDELIVERY
+#define ISELECT_IMSIC_LAST ISELECT_IMSIC_EIE63
+
+/* IMSIC bits (AIA) */
+#define IMSIC_TOPEI_IID_SHIFT 16
+#define IMSIC_TOPEI_IID_MASK 0x7ff
+#define IMSIC_TOPEI_IPIRO_MASK 0x7ff
+#define IMSIC_EIPx_BITS 32
+#define IMSIC_EIEx_BITS 32
+
+/* MTOPI and STOPI bits (AIA) */
+#define TOPI_IID_SHIFT 16
+#define TOPI_IID_MASK 0xfff
+#define TOPI_IPRIO_MASK 0xff
+
+/* Interrupt priority bits (AIA) */
+#define IPRIO_IRQ_BITS 8
+#define IPRIO_MMAXIPRIO 255
+#define IPRIO_DEFAULT_MMAXIPRIO 15
+#define IPRIO_DEFAULT_VS (IPRIO_DEFAULT_MMAXIPRIO - 4)
+#define IPRIO_DEFAULT_SGEXT (IPRIO_DEFAULT_MMAXIPRIO - 5)
+#define IPRIO_DEFAULT_S (IPRIO_DEFAULT_MMAXIPRIO - 6)
+#define IPRIO_DEFAULT_M (IPRIO_DEFAULT_MMAXIPRIO - 7)
+#define IPRIO_DEFAULT_U(_i) (((_i) >> 4) & 0x3)
+#define IPRIO_DEFAULT_L(_i) ((_i) & 0xf)
+#define IPRIO_DEFAULT_16_23(_i) \
+ (IPRIO_DEFAULT_MMAXIPRIO - (IPRIO_DEFAULT_L(_i) >> 1))
+#define IPRIO_DEFAULT_24_31(_i) \
+ (IPRIO_DEFAULT_MMAXIPRIO - (4 + (IPRIO_DEFAULT_L(_i) >> 1)))
+#define IPRIO_DEFAULT_32_47(_i) \
+ (IPRIO_DEFAULT_MMAXIPRIO - (IPRIO_DEFAULT_L(_i) >> 2))
+#define IPRIO_DEFAULT_48_63(_i) \
+ (IPRIO_DEFAULT_MMAXIPRIO - (8 + (IPRIO_DEFAULT_L(_i) >> 2)))
+
+/* HVICONTROL bits (AIA) */
+#define HVICONTROL_VTI 0x40000000
+#define HVICONTROL_IID_MASK 0xfff
+#define HVICONTROL_IID_SHIFT 16
+#define HVICONTROL_IPRIO_MASK 0xff
+#define HVICONTROL_VALID_MASK \
+ (HVICONTROL_VTI | \
+ (HVICONTROL_IID_MASK << HVICONTROL_IID_SHIFT) | \
+ HVICONTROL_IPRIO_MASK)
+
#endif
--
2.25.1