[Bug 1885350] Re: RISCV dynamic rounding mode is not behaving correctly

[Thomas Huth]

The QEMU project is currently moving its bug tracking to another system.
Is there still anything left to do here? If so, please provide the test case 
and switch the state back to "New" or "Confirmed", or open a new ticket in the 
new bug tracker here: https://gitlab.com/qemu-project/qemu/-/issues

** Changed in: qemu
     Assignee: Alistair Francis (alistair2323) => (unassigned)

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https://bugs.launchpad.net/bugs/1885350

Title:
  RISCV dynamic rounding mode is not behaving correctly

Status in QEMU:
  Incomplete

Bug description:
  Hello,

  I’ve gone through the RISC-V code in latest QEMU release
  (qemu-5.0.0-rc2) and when checking the Floating point encodings I
  found the rounding mode is only updated if the opcode field “rm” is
  changed “ctx->frm == rm”. But according to RISC-V Volume I:
  Unprivileged ISA, there’s a dynamic mode when rm=7 where the rounding
  mode is set with frm value.

  So for the same rm value (=7) and when changing frm value seeking
  different rounding modes, and according to the below code, the
  rounding mode won’t be updated. Please correct me if I got this
  implementation wrong.

  static void gen_set_rm(DisasContext *ctx, int rm)
  {
      TCGv_i32 t0;
      if (ctx->frm == rm) {
          return;
      }
      ctx->frm = rm;
      t0 = tcg_const_i32(rm);
      gen_helper_set_rounding_mode(cpu_env, t0);
      tcg_temp_free_i32(t0);
  }

  
  My testcase:
  I set statically the rm field in the instruction to 7 and before this 
execution I changed the value of frm field in fcsr register. For the 1st time 
it worked (according to the code above, the rm is updated so the round mode 
will also be updated). But when changing fcsr register an re-execute the 
instruction, there's no difference and the rounding mode is the same like the 
previous frm value.

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