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[PATCH v7 55/92] target/arm: Implement SVE2 saturating multiply-add high
From: |
Richard Henderson |
Subject: |
[PATCH v7 55/92] target/arm: Implement SVE2 saturating multiply-add high (indexed) |
Date: |
Mon, 24 May 2021 18:03:21 -0700 |
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper-sve.h | 14 ++++++++++++++
target/arm/sve.decode | 8 ++++++++
target/arm/sve_helper.c | 36 ++++++++++++++++++++++++++++++++++++
target/arm/translate-sve.c | 8 ++++++++
4 files changed, 66 insertions(+)
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index 7e99dcd119..fe67574741 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -2665,3 +2665,17 @@ DEF_HELPER_FLAGS_5(sve2_sqrdcmlah_zzzz_d,
TCG_CALL_NO_RWG,
DEF_HELPER_FLAGS_6(fmmla_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr,
i32)
DEF_HELPER_FLAGS_6(fmmla_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr,
i32)
+
+DEF_HELPER_FLAGS_5(sve2_sqrdmlah_idx_h, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve2_sqrdmlah_idx_s, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve2_sqrdmlah_idx_d, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_idx_h, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_idx_s, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_idx_d, TCG_CALL_NO_RWG,
+ void, ptr, ptr, ptr, ptr, i32)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 9bfaf737b7..1956d96ad5 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -791,6 +791,14 @@ MLS_zzxz_h 01000100 0. 1 ..... 000011 ..... .....
@rrxr_3 esz=1
MLS_zzxz_s 01000100 10 1 ..... 000011 ..... ..... @rrxr_2 esz=2
MLS_zzxz_d 01000100 11 1 ..... 000011 ..... ..... @rrxr_1 esz=3
+# SVE2 saturating multiply-add high (indexed)
+SQRDMLAH_zzxz_h 01000100 0. 1 ..... 000100 ..... ..... @rrxr_3 esz=1
+SQRDMLAH_zzxz_s 01000100 10 1 ..... 000100 ..... ..... @rrxr_2 esz=2
+SQRDMLAH_zzxz_d 01000100 11 1 ..... 000100 ..... ..... @rrxr_1 esz=3
+SQRDMLSH_zzxz_h 01000100 0. 1 ..... 000101 ..... ..... @rrxr_3 esz=1
+SQRDMLSH_zzxz_s 01000100 10 1 ..... 000101 ..... ..... @rrxr_2 esz=2
+SQRDMLSH_zzxz_d 01000100 11 1 ..... 000101 ..... ..... @rrxr_1 esz=3
+
# SVE2 integer multiply (indexed)
MUL_zzx_h 01000100 0. 1 ..... 111110 ..... ..... @rrx_3 esz=1
MUL_zzx_s 01000100 10 1 ..... 111110 ..... ..... @rrx_2 esz=2
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index fa96e28639..11d4a2a722 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -1499,6 +1499,42 @@ DO_CMLA_FUNC(sve2_sqrdcmlah_zzzz_d, int64_t, ,
DO_SQRDMLAH_D)
#undef DO_SQRDMLAH_S
#undef DO_SQRDMLAH_D
+#define DO_ZZXZ(NAME, TYPE, H, OP) \
+void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, uint32_t desc) \
+{ \
+ intptr_t oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \
+ intptr_t i, j, idx = simd_data(desc); \
+ TYPE *d = vd, *a = va, *n = vn, *m = (TYPE *)vm + H(idx); \
+ for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \
+ TYPE mm = m[i]; \
+ for (j = 0; j < segment; j++) { \
+ d[i + j] = OP(n[i + j], mm, a[i + j]); \
+ } \
+ } \
+}
+
+#define DO_SQRDMLAH_H(N, M, A) \
+ ({ uint32_t discard; do_sqrdmlah_h(N, M, A, false, true, &discard); })
+#define DO_SQRDMLAH_S(N, M, A) \
+ ({ uint32_t discard; do_sqrdmlah_s(N, M, A, false, true, &discard); })
+#define DO_SQRDMLAH_D(N, M, A) do_sqrdmlah_d(N, M, A, false, true)
+
+DO_ZZXZ(sve2_sqrdmlah_idx_h, int16_t, H2, DO_SQRDMLAH_H)
+DO_ZZXZ(sve2_sqrdmlah_idx_s, int32_t, H4, DO_SQRDMLAH_S)
+DO_ZZXZ(sve2_sqrdmlah_idx_d, int64_t, , DO_SQRDMLAH_D)
+
+#define DO_SQRDMLSH_H(N, M, A) \
+ ({ uint32_t discard; do_sqrdmlah_h(N, M, A, true, true, &discard); })
+#define DO_SQRDMLSH_S(N, M, A) \
+ ({ uint32_t discard; do_sqrdmlah_s(N, M, A, true, true, &discard); })
+#define DO_SQRDMLSH_D(N, M, A) do_sqrdmlah_d(N, M, A, true, true)
+
+DO_ZZXZ(sve2_sqrdmlsh_idx_h, int16_t, H2, DO_SQRDMLSH_H)
+DO_ZZXZ(sve2_sqrdmlsh_idx_s, int32_t, H4, DO_SQRDMLSH_S)
+DO_ZZXZ(sve2_sqrdmlsh_idx_d, int64_t, , DO_SQRDMLSH_D)
+
+#undef DO_ZZXZ
+
#define DO_BITPERM(NAME, TYPE, OP) \
void HELPER(NAME)(void *vd, void *vn, void *vm, uint32_t desc) \
{ \
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 39a6839de4..b31a4d1fb2 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -3895,6 +3895,14 @@ DO_SVE2_RRXR(trans_MLS_zzxz_h, gen_helper_gvec_mls_idx_h)
DO_SVE2_RRXR(trans_MLS_zzxz_s, gen_helper_gvec_mls_idx_s)
DO_SVE2_RRXR(trans_MLS_zzxz_d, gen_helper_gvec_mls_idx_d)
+DO_SVE2_RRXR(trans_SQRDMLAH_zzxz_h, gen_helper_sve2_sqrdmlah_idx_h)
+DO_SVE2_RRXR(trans_SQRDMLAH_zzxz_s, gen_helper_sve2_sqrdmlah_idx_s)
+DO_SVE2_RRXR(trans_SQRDMLAH_zzxz_d, gen_helper_sve2_sqrdmlah_idx_d)
+
+DO_SVE2_RRXR(trans_SQRDMLSH_zzxz_h, gen_helper_sve2_sqrdmlsh_idx_h)
+DO_SVE2_RRXR(trans_SQRDMLSH_zzxz_s, gen_helper_sve2_sqrdmlsh_idx_s)
+DO_SVE2_RRXR(trans_SQRDMLSH_zzxz_d, gen_helper_sve2_sqrdmlsh_idx_d)
+
#undef DO_SVE2_RRXR
/*
--
2.25.1
- [PATCH v7 39/92] target/arm: Implement SVE2 RADDHNB, RADDHNT, (continued)
- [PATCH v7 39/92] target/arm: Implement SVE2 RADDHNB, RADDHNT, Richard Henderson, 2021/05/24
- [PATCH v7 40/92] target/arm: Implement SVE2 SUBHNB, SUBHNT, Richard Henderson, 2021/05/24
- [PATCH v7 41/92] target/arm: Implement SVE2 RSUBHNB, RSUBHNT, Richard Henderson, 2021/05/24
- [PATCH v7 42/92] target/arm: Implement SVE2 HISTCNT, HISTSEG, Richard Henderson, 2021/05/24
- [PATCH v7 43/92] target/arm: Implement SVE2 XAR, Richard Henderson, 2021/05/24
- [PATCH v7 44/92] target/arm: Implement SVE2 scatter store insns, Richard Henderson, 2021/05/24
- [PATCH v7 64/92] target/arm: Macroize helper_gvec_{s,u}dot_{b,h}, Richard Henderson, 2021/05/24
- [PATCH v7 48/92] target/arm: Use correct output type for gvec_sdot_*_b, Richard Henderson, 2021/05/24
- [PATCH v7 49/92] target/arm: Pass separate addend to {U, S}DOT helpers, Richard Henderson, 2021/05/24
- [PATCH v7 56/92] target/arm: Implement SVE2 saturating multiply-add (indexed), Richard Henderson, 2021/05/24
- [PATCH v7 55/92] target/arm: Implement SVE2 saturating multiply-add high (indexed),
Richard Henderson <=
- [PATCH v7 59/92] target/arm: Implement SVE2 saturating multiply high (indexed), Richard Henderson, 2021/05/24
- [PATCH v7 47/92] target/arm: Implement SVE2 SPLICE, EXT, Richard Henderson, 2021/05/24
- [PATCH v7 60/92] target/arm: Implement SVE2 multiply-add long (indexed), Richard Henderson, 2021/05/24
- [PATCH v7 68/92] target/arm: Implement SVE2 crypto unary operations, Richard Henderson, 2021/05/24
- [PATCH v7 52/92] target/arm: Split out formats for 3 vectors + 1 index, Richard Henderson, 2021/05/24
- [PATCH v7 45/92] target/arm: Implement SVE2 gather load insns, Richard Henderson, 2021/05/24
- [PATCH v7 58/92] target/arm: Implement SVE2 signed saturating doubling multiply high, Richard Henderson, 2021/05/24
- [PATCH v7 61/92] target/arm: Implement SVE2 integer multiply long (indexed), Richard Henderson, 2021/05/24
- [PATCH v7 66/92] target/arm: Implement SVE mixed sign dot product (indexed), Richard Henderson, 2021/05/24
- [PATCH v7 67/92] target/arm: Implement SVE mixed sign dot product, Richard Henderson, 2021/05/24