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[PATCH v7 77/92] target/arm: Tidy do_ldrq
From: |
Richard Henderson |
Subject: |
[PATCH v7 77/92] target/arm: Tidy do_ldrq |
Date: |
Mon, 24 May 2021 18:03:43 -0700 |
Use tcg_constant_i32 for passing the simd descriptor,
as this hashed value does not need to be freed.
Rename dofs to doff to match poff.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-sve.c | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 54c50349ab..a213450583 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -5580,13 +5580,9 @@ static void do_ldrq(DisasContext *s, int zt, int pg,
TCGv_i64 addr, int dtype)
{
unsigned vsz = vec_full_reg_size(s);
TCGv_ptr t_pg;
- TCGv_i32 t_desc;
- int desc, poff;
+ int poff;
/* Load the first quadword using the normal predicated load helpers. */
- desc = simd_desc(16, 16, zt);
- t_desc = tcg_const_i32(desc);
-
poff = pred_full_reg_offset(s, pg);
if (vsz > 16) {
/*
@@ -5611,15 +5607,14 @@ static void do_ldrq(DisasContext *s, int zt, int pg,
TCGv_i64 addr, int dtype)
gen_helper_gvec_mem *fn
= ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0];
- fn(cpu_env, t_pg, addr, t_desc);
+ fn(cpu_env, t_pg, addr, tcg_constant_i32(simd_desc(16, 16, zt)));
tcg_temp_free_ptr(t_pg);
- tcg_temp_free_i32(t_desc);
/* Replicate that first quadword. */
if (vsz > 16) {
- unsigned dofs = vec_full_reg_offset(s, zt);
- tcg_gen_gvec_dup_mem(4, dofs + 16, dofs, vsz - 16, vsz - 16);
+ int doff = vec_full_reg_offset(s, zt);
+ tcg_gen_gvec_dup_mem(4, doff + 16, doff, vsz - 16, vsz - 16);
}
}
--
2.25.1
- [PATCH v7 63/92] target/arm: Implement SVE2 complex integer dot product, (continued)
- [PATCH v7 63/92] target/arm: Implement SVE2 complex integer dot product, Richard Henderson, 2021/05/24
- [PATCH v7 53/92] target/arm: Implement SVE2 integer multiply (indexed), Richard Henderson, 2021/05/24
- [PATCH v7 62/92] target/arm: Implement SVE2 complex integer multiply-add (indexed), Richard Henderson, 2021/05/24
- [PATCH v7 71/92] target/arm: Implement SVE2 TBL, TBX, Richard Henderson, 2021/05/24
- [PATCH v7 46/92] target/arm: Implement SVE2 FMMLA, Richard Henderson, 2021/05/24
- [PATCH v7 72/92] target/arm: Implement SVE2 FCVTNT, Richard Henderson, 2021/05/24
- [PATCH v7 74/92] target/arm: Implement SVE2 FCVTXNT, FCVTX, Richard Henderson, 2021/05/24
- [PATCH v7 75/92] target/arm: Implement SVE2 FLOGB, Richard Henderson, 2021/05/24
- [PATCH v7 73/92] target/arm: Implement SVE2 FCVTLT, Richard Henderson, 2021/05/24
- [PATCH v7 76/92] target/arm: Share table of sve load functions, Richard Henderson, 2021/05/24
- [PATCH v7 77/92] target/arm: Tidy do_ldrq,
Richard Henderson <=
- [PATCH v7 79/92] target/arm: Implement 128-bit ZIP, UZP, TRN, Richard Henderson, 2021/05/24
- [PATCH v7 78/92] target/arm: Implement SVE2 LD1RO, Richard Henderson, 2021/05/24
- [PATCH v7 82/92] target/arm: Implement SVE2 fp multiply-add long, Richard Henderson, 2021/05/24
- [PATCH v7 80/92] target/arm: Implement SVE2 bitwise shift immediate, Richard Henderson, 2021/05/24
- [PATCH v7 81/92] target/arm: Move endian adjustment macros to vec_internal.h, Richard Henderson, 2021/05/24
- [PATCH v7 83/92] target/arm: Implement aarch64 SUDOT, USDOT, Richard Henderson, 2021/05/24
- [PATCH v7 85/92] target/arm: Remove unused fpst from VDOT_scalar, Richard Henderson, 2021/05/24
- [PATCH v7 87/92] target/arm: Split out do_neon_ddda, Richard Henderson, 2021/05/24
- [PATCH v7 84/92] target/arm: Split out do_neon_ddda_fpst, Richard Henderson, 2021/05/24
- [PATCH v7 88/92] target/arm: Split decode of VSDOT and VUDOT, Richard Henderson, 2021/05/24