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Re: [PATCH v2 0/9] accel/tcg: Add tlb_flush interface for a range of pag
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From: |
Peter Maydell |
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Subject: |
Re: [PATCH v2 0/9] accel/tcg: Add tlb_flush interface for a range of pages |
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Date: |
Tue, 25 May 2021 10:55:05 +0100 |
On Tue, 25 May 2021 at 08:56, Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> ping?
I talked to RTH about this yesterday; I actually have it in
my target-arm queue and reviewed. I'm just waiting for Richard
to supply some commit messages to fill in the bits you left
as placeholders/blank...
thanks
-- PMM
- [PATCH 6/9] accel/tlb: Add tlb_flush_range_by_mmuidx_all_cpus_synced(), (continued)
- [PATCH 6/9] accel/tlb: Add tlb_flush_range_by_mmuidx_all_cpus_synced(), Philippe Mathieu-Daudé, 2021/05/09
- [PATCH 7/9] accel/tcg: Rename tlb_flush_page_bits -> range]_by_mmuidx_async_0, Philippe Mathieu-Daudé, 2021/05/09
- [PATCH 8/9] accel/tlb: Rename tlb_flush_[page_bits > range]_by_mmuidx_async_[2 > 1], Philippe Mathieu-Daudé, 2021/05/09
- [PATCH 9/9] accel/tcg: Remove tlb_flush_page_bits_by_mmuidx_async_1() ???, Philippe Mathieu-Daudé, 2021/05/09
- Re: [PATCH 0/9] accel/tcg: Add tlb_flush interface for a range of pages, Philippe Mathieu-Daudé, 2021/05/09
- Re: [PATCH 0/9] accel/tcg: Add tlb_flush interface for a range of pages, Peter Maydell, 2021/05/25