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Re: [PATCH v3 4/8] hw/intc: GICv3 ITS Command processing
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From: |
shashi . mallela |
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Subject: |
Re: [PATCH v3 4/8] hw/intc: GICv3 ITS Command processing |
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Date: |
Tue, 25 May 2021 13:57:53 -0400 |
Have taken care of all comments ,except one with my inline response
On Tue, 2021-05-18 at 16:49 +0100, Peter Maydell wrote:
> On Fri, 30 Apr 2021 at 00:42, Shashi Mallela <
> shashi.mallela@linaro.org> wrote:
> > Added ITS command queue handling for MAPTI,MAPI commands,handled
> > ITS
> > translation which triggers an LPI via INT command as well as write
> > to GITS_TRANSLATER register,defined enum to differentiate between
> > ITS
> > command interrupt trigger and GITS_TRANSLATER based interrupt
> > trigger.
> > Each of these commands make use of other functionalities
> > implemented to
> > get device table entry,collection table entry or interrupt
> > translation
> > table entry required for their processing.
> >
> > Signed-off-by: Shashi Mallela <shashi.mallela@linaro.org>
> > ---
> > hw/intc/arm_gicv3_its.c | 346
> > ++++++++++++++++++++++++++++-
> > hw/intc/gicv3_internal.h | 12 +
> > include/hw/intc/arm_gicv3_common.h | 2 +
> > 3 files changed, 359 insertions(+), 1 deletion(-)
> >
> > diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c
> > index 7cb465813a..98c984dd22 100644
> > --- a/hw/intc/arm_gicv3_its.c
> > +++ b/hw/intc/arm_gicv3_its.c
> > @@ -28,6 +28,156 @@ struct GICv3ITSClass {
> > void (*parent_reset)(DeviceState *dev);
> > };
> >
> > +typedef enum ItsCmdType {
> > + NONE = 0, /* internal indication for GITS_TRANSLATER write */
> > + CLEAR = 1,
> > + DISCARD = 2,
> > + INT = 3,
> > +} ItsCmdType;
> > +
> > +static bool get_cte(GICv3ITSState *s, uint16_t icid, uint64_t
> > *cte,
> > + MemTxResult *res)
> > +{
> > + AddressSpace *as = &s->gicv3->dma_as;
> > + uint64_t l2t_addr;
> > + uint64_t value;
> > + bool valid_l2t;
> > + uint32_t l2t_id;
> > + uint32_t max_l2_entries;
> > + bool status = false;
> > +
> > + if (s->ct.indirect) {
> > + l2t_id = icid / (s->ct.page_sz / L1TABLE_ENTRY_SIZE);
> > +
> > + value = address_space_ldq_le(as,
> > + s->ct.base_addr +
> > + (l2t_id *
> > L1TABLE_ENTRY_SIZE),
> > + MEMTXATTRS_UNSPECIFIED, res);
> > +
> > + if (*res == MEMTX_OK) {
> > + valid_l2t = (value >> VALID_SHIFT) & VALID_MASK;
> > +
> > + if (valid_l2t) {
> > + max_l2_entries = s->ct.page_sz / s->ct.entry_sz;
> > +
> > + l2t_addr = value & ((1ULL << 51) - 1);
> > +
> > + *cte = address_space_ldq_le(as, l2t_addr +
> > + ((icid % max_l2_entries) *
> > GITS_CTE_SIZE),
> > + MEMTXATTRS_UNSPECIFIED, res);
> > + }
> > + }
> > + } else {
> > + /* Flat level table */
> > + *cte = address_space_ldq_le(as, s->ct.base_addr +
> > + (icid * GITS_CTE_SIZE),
> > + MEMTXATTRS_UNSPECIFIED,
> > res);
> > + }
> > +
> > + if (*cte & VALID_MASK) {
> > + status = true;
> > + }
> > +
> > + return status;
> > +}
> > +
> > +static MemTxResult update_ite(GICv3ITSState *s, uint32_t eventid,
> > uint64_t dte,
> > + uint64_t itel, uint32_t iteh)
> > +{
> > + AddressSpace *as = &s->gicv3->dma_as;
> > + uint64_t itt_addr;
> > + MemTxResult res = MEMTX_OK;
> > +
> > + itt_addr = (dte >> 6ULL) & ITTADDR_MASK;
> > + itt_addr <<= ITTADDR_SHIFT; /* 256 byte aligned */
> > +
> > + address_space_stq_le(as, itt_addr + (eventid *
> > sizeof(uint64_t)),
> > + itel, MEMTXATTRS_UNSPECIFIED, &res);
> > +
> > + if (res == MEMTX_OK) {
> > + address_space_stl_le(as, itt_addr + ((eventid +
> > sizeof(uint64_t)) *
> > + sizeof(uint32_t)), iteh,
> > MEMTXATTRS_UNSPECIFIED,
> > + &res);
> > + }
> > + return res;
> > +}
> > +
> > +static bool get_ite(GICv3ITSState *s, uint32_t eventid, uint64_t
> > dte,
> > + uint16_t *icid, uint32_t *pIntid,
> > MemTxResult *res)
> > +{
> > + AddressSpace *as = &s->gicv3->dma_as;
> > + uint64_t itt_addr;
> > + bool status = false;
> > + uint64_t itel = 0;
> > + uint32_t iteh = 0;
> > +
> > + itt_addr = (dte >> 6ULL) & ITTADDR_MASK;
> > + itt_addr <<= ITTADDR_SHIFT; /* 256 byte aligned */
> > +
> > + itel = address_space_ldq_le(as, itt_addr + (eventid *
> > sizeof(uint64_t)),
> > + MEMTXATTRS_UNSPECIFIED, res);
> > +
> > + if (*res == MEMTX_OK) {
> > + iteh = address_space_ldl_le(as, itt_addr + ((eventid +
> > + sizeof(uint64_t)) *
> > sizeof(uint32_t)),
> > + MEMTXATTRS_UNSPECIFIED, res);
> > +
> > + if (*res == MEMTX_OK) {
> > + if (itel & VALID_MASK) {
> > + if ((itel >> ITE_ENTRY_INTTYPE_SHIFT) &
> > GITS_TYPE_PHYSICAL) {
> > + *pIntid = (itel >> ITE_ENTRY_INTID_SHIFT) &
> > + ITE_ENTRY_INTID_MASK;
> > + *icid = iteh & ITE_ENTRY_ICID_MASK;
> > + status = true;
> > + }
> > + }
> > + }
> > + }
> > + return status;
> > +}
> > +
> > +static uint64_t get_dte(GICv3ITSState *s, uint32_t devid,
> > MemTxResult *res)
> > +{
> > + AddressSpace *as = &s->gicv3->dma_as;
> > + uint64_t l2t_addr;
> > + uint64_t value;
> > + bool valid_l2t;
> > + uint32_t l2t_id;
> > + uint32_t max_l2_entries;
> > +
> > + if (s->dt.indirect) {
> > + l2t_id = devid / (s->dt.page_sz / L1TABLE_ENTRY_SIZE);
> > +
> > + value = address_space_ldq_le(as,
> > + s->dt.base_addr +
> > + (l2t_id *
> > L1TABLE_ENTRY_SIZE),
> > + MEMTXATTRS_UNSPECIFIED, res);
> > +
> > + if (*res == MEMTX_OK) {
> > + valid_l2t = (value >> VALID_SHIFT) & VALID_MASK;
> > +
> > + if (valid_l2t) {
> > + max_l2_entries = s->dt.page_sz / s->dt.entry_sz;
> > +
> > + l2t_addr = value & ((1ULL << 51) - 1);
> > +
> > + value = 0;
>
> This assignment is pointless because we assign again to value
> immediately
> afterwards.
>
> > + value = address_space_ldq_le(as, l2t_addr +
> > + ((devid % max_l2_entries) *
> > GITS_DTE_SIZE),
> > + MEMTXATTRS_UNSPECIFIED, res);
> > + }
> > + }
> > + } else {
> > + /* Flat level table */
> > + value = 0;
>
> Ditto.
>
> > + value = address_space_ldq_le(as, s->dt.base_addr +
> > + (devid *
> > GITS_DTE_SIZE),
> > + MEMTXATTRS_UNSPECIFIED, res);
> > + }
> > +
> > + return value;
> > +}
> > +
> > static MemTxResult process_sync(GICv3ITSState *s, uint32_t offset)
> > {
> > AddressSpace *as = &s->gicv3->dma_as;
> > @@ -55,6 +205,182 @@ static MemTxResult process_sync(GICv3ITSState
> > *s, uint32_t offset)
> > return res;
> > }
> >
> > +static MemTxResult process_int(GICv3ITSState *s, uint64_t value,
> > + uint32_t offset, ItsCmdType cmd)
> > +{
> > + AddressSpace *as = &s->gicv3->dma_as;
> > + uint32_t devid, eventid;
> > + MemTxResult res = MEMTX_OK;
> > + bool dte_valid;
> > + uint64_t dte = 0;
> > + uint32_t max_eventid;
> > + uint16_t icid = 0;
> > + uint32_t pIntid = 0;
> > + bool ite_valid = false;
> > + uint64_t cte = 0;
> > + bool cte_valid = false;
> > + uint64_t itel = 0;
> > + uint32_t iteh = 0;
> > +
> > + if (cmd == NONE) {
> > + devid = offset;
> > + } else {
> > + devid = (value >> DEVID_SHIFT) & DEVID_MASK;
> > +
> > + offset += NUM_BYTES_IN_DW;
> > + value = address_space_ldq_le(as, s->cq.base_addr + offset,
> > + MEMTXATTRS_UNSPECIFIED, &res);
> > + }
> > +
> > + if (res != MEMTX_OK) {
> > + return res;
> > + }
> > +
> > + eventid = (value & EVENTID_MASK);
> > +
> > + dte = get_dte(s, devid, &res);
> > +
> > + if (res != MEMTX_OK) {
> > + return res;
> > + }
> > + dte_valid = dte & VALID_MASK;
> > +
> > + if (dte_valid) {
> > + max_eventid = (1UL << (((dte >> 1U) & SIZE_MASK) + 1));
> > +
> > + ite_valid = get_ite(s, eventid, dte, &icid, &pIntid,
> > &res);
> > +
> > + if (res != MEMTX_OK) {
> > + return res;
> > + }
> > +
> > + if (ite_valid) {
> > + cte_valid = get_cte(s, icid, &cte, &res);
> > + }
> > +
> > + if (res != MEMTX_OK) {
> > + return res;
> > + }
> > + }
> > +
> > + if ((devid > s->dt.max_devids) || !dte_valid || !ite_valid ||
> > + !cte_valid || (eventid > max_eventid)) {
> > + qemu_log_mask(LOG_GUEST_ERROR,
> > + "%s: invalid interrupt translation table attributes "
> > + "devid %d or eventid %d\n",
> > + __func__, devid, eventid);
> > + /*
> > + * in this implementation,in case of error
> > + * we ignore this command and move onto the next
> > + * command in the queue
> > + */
>
> ...but we could just return an error from this function and
> get the 'stall' behaviour. It would be more consistent to just
> stall for everything, if we're going to be stalling for various
> kinds of "failed to read memory" anyway. (Same for some instances
> of this in the previous patches.)
>
> The intent here was to chose the spec defined options to 'ignore and
> move on' for all ITS command specific errors but differentiate system
> errors like mem read/write with 'implementation defined' STALL.
>
>
> > + } else {
> > + /*
> > + * Current implementation only supports rdbase == procnum
> > + * Hence rdbase physical address is ignored
> > + */
> > + if (cmd == DISCARD) {
> > + /* remove mapping from interrupt translation table */
> > + res = update_ite(s, eventid, dte, itel, iteh);
> > + }
> > + }
> > +
> > + if (cmd != NONE) {
> > + offset += NUM_BYTES_IN_DW;
> > + offset += NUM_BYTES_IN_DW;
>
> More dead increments.
>
> > + }
> > +
> > + return res;
> > +}
> > +
>
> -- PMM