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[PULL 30/31] target/mips: Fold jazz behaviour into mips_cpu_do_transacti
From: |
Richard Henderson |
Subject: |
[PULL 30/31] target/mips: Fold jazz behaviour into mips_cpu_do_transaction_failed |
Date: |
Wed, 26 May 2021 16:47:09 -0700 |
Add a flag to MIPSCPUClass in order to avoid needing to
replace mips_tcg_ops.do_transaction_failed.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20210227232519.222663-2-richard.henderson@linaro.org>
---
target/mips/cpu-qom.h | 3 +++
hw/mips/jazz.c | 35 +++--------------------------------
target/mips/tcg/op_helper.c | 3 ++-
3 files changed, 8 insertions(+), 33 deletions(-)
diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h
index 826ab13019..dda0c911fa 100644
--- a/target/mips/cpu-qom.h
+++ b/target/mips/cpu-qom.h
@@ -47,6 +47,9 @@ struct MIPSCPUClass {
DeviceRealize parent_realize;
DeviceReset parent_reset;
const struct mips_def_t *cpu_def;
+
+ /* Used for the jazz board to modify mips_cpu_do_transaction_failed. */
+ bool no_data_aborts;
};
diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c
index dba2088ed1..1e1cf8154e 100644
--- a/hw/mips/jazz.c
+++ b/hw/mips/jazz.c
@@ -119,30 +119,6 @@ static const MemoryRegionOps dma_dummy_ops = {
#define MAGNUM_BIOS_SIZE
\
(BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
-#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
-static void (*real_do_transaction_failed)(CPUState *cpu, hwaddr physaddr,
- vaddr addr, unsigned size,
- MMUAccessType access_type,
- int mmu_idx, MemTxAttrs attrs,
- MemTxResult response,
- uintptr_t retaddr);
-
-static void mips_jazz_do_transaction_failed(CPUState *cs, hwaddr physaddr,
- vaddr addr, unsigned size,
- MMUAccessType access_type,
- int mmu_idx, MemTxAttrs attrs,
- MemTxResult response,
- uintptr_t retaddr)
-{
- if (access_type != MMU_INST_FETCH) {
- /* ignore invalid access (ie do not raise exception) */
- return;
- }
- (*real_do_transaction_failed)(cs, physaddr, addr, size, access_type,
- mmu_idx, attrs, response, retaddr);
-}
-#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
-
static void mips_jazz_init(MachineState *machine,
enum jazz_model_e jazz_model)
{
@@ -151,7 +127,7 @@ static void mips_jazz_init(MachineState *machine,
int bios_size, n;
Clock *cpuclk;
MIPSCPU *cpu;
- CPUClass *cc;
+ MIPSCPUClass *mcc;
CPUMIPSState *env;
qemu_irq *i8259;
rc4030_dma *dmas;
@@ -198,8 +174,6 @@ static void mips_jazz_init(MachineState *machine,
* However, we can't simply add a global memory region to catch
* everything, as this would make all accesses including instruction
* accesses be ignored and not raise exceptions.
- * So instead we hijack the do_transaction_failed method on the CPU, and
- * do not raise exceptions for data access.
*
* NOTE: this behaviour of raising exceptions for bad instruction
* fetches but not bad data accesses was added in commit 54e755588cf1e9
@@ -209,11 +183,8 @@ static void mips_jazz_init(MachineState *machine,
* we could replace this hijacking of CPU methods with a simple global
* memory region that catches all memory accesses, as we do on Malta.
*/
- cc = CPU_GET_CLASS(cpu);
-#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
- real_do_transaction_failed = cc->tcg_ops->do_transaction_failed;
- cc->tcg_ops->do_transaction_failed = mips_jazz_do_transaction_failed;
-#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
+ mcc = MIPS_CPU_GET_CLASS(cpu);
+ mcc->no_data_aborts = true;
/* allocate RAM */
memory_region_add_subregion(address_space, 0, machine->ram);
diff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c
index ce1549c985..fafbf1faca 100644
--- a/target/mips/tcg/op_helper.c
+++ b/target/mips/tcg/op_helper.c
@@ -409,11 +409,12 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr
physaddr,
MemTxResult response, uintptr_t retaddr)
{
MIPSCPU *cpu = MIPS_CPU(cs);
+ MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
CPUMIPSState *env = &cpu->env;
if (access_type == MMU_INST_FETCH) {
do_raise_exception(env, EXCP_IBE, retaddr);
- } else {
+ } else if (!mcc->no_data_aborts) {
do_raise_exception(env, EXCP_DBE, retaddr);
}
}
--
2.25.1
- [PULL 04/31] exec/memory_ldst_phys: Use correct type sizes, (continued)
- [PULL 04/31] exec/memory_ldst_phys: Use correct type sizes, Richard Henderson, 2021/05/26
- [PULL 15/31] cpu: Directly use cpu_write_elf*() fallback handlers in place, Richard Henderson, 2021/05/26
- [PULL 20/31] cpu: Move AVR target vmsd field from CPUClass to DeviceClass, Richard Henderson, 2021/05/26
- [PULL 26/31] cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps, Richard Henderson, 2021/05/26
- [PULL 17/31] cpu: Directly use get_memory_mapping() fallback handlers in place, Richard Henderson, 2021/05/26
- [PULL 18/31] cpu: Assert DeviceClass::vmsd is NULL on user emulation, Richard Henderson, 2021/05/26
- [PULL 19/31] cpu: Rename CPUClass vmsd -> legacy_vmsd, Richard Henderson, 2021/05/26
- [PULL 22/31] cpu: Move CPUClass::vmsd to SysemuCPUOps, Richard Henderson, 2021/05/26
- [PULL 23/31] cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps, Richard Henderson, 2021/05/26
- [PULL 24/31] cpu: Move CPUClass::get_crash_info to SysemuCPUOps, Richard Henderson, 2021/05/26
- [PULL 30/31] target/mips: Fold jazz behaviour into mips_cpu_do_transaction_failed,
Richard Henderson <=
- [PULL 21/31] cpu: Introduce SysemuCPUOps structure, Richard Henderson, 2021/05/26
- [PULL 25/31] cpu: Move CPUClass::write_elf* to SysemuCPUOps, Richard Henderson, 2021/05/26
- [PULL 27/31] cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps, Richard Henderson, 2021/05/26
- [PULL 28/31] cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps, Richard Henderson, 2021/05/26
- [PULL 31/31] hw/core: Constify TCGCPUOps, Richard Henderson, 2021/05/26
- [PULL 29/31] cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps, Richard Henderson, 2021/05/26
- Re: [PULL 00/31] tcg patch queue, Peter Maydell, 2021/05/28