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[PULL 42/42] target/ppc: fix single-step exception regression
From: |
David Gibson |
Subject: |
[PULL 42/42] target/ppc: fix single-step exception regression |
Date: |
Thu, 3 Jun 2021 18:22:31 +1000 |
From: Luis Pires <luis.pires@eldorado.org.br>
Commit 6086c75 (target/ppc: Replace POWERPC_EXCP_BRANCH with
DISAS_NORETURN) broke the generation of exceptions when
CPU_SINGLE_STEP or CPU_BRANCH_STEP were set, due to nip always being
reset to the address of the current instruction.
This fix leaves nip untouched when generating the exception.
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
Reported-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20210602125103.332793-1-luis.pires@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 95e4d9b815..f65d1e81ea 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -4320,8 +4320,7 @@ static void gen_lookup_and_goto_ptr(DisasContext *ctx)
if (sse & GDBSTUB_SINGLE_STEP) {
gen_debug_exception(ctx);
} else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) {
- uint32_t excp = gen_prep_dbgex(ctx);
- gen_exception(ctx, excp);
+ gen_helper_raise_exception(cpu_env,
tcg_constant_i32(gen_prep_dbgex(ctx)));
} else {
tcg_gen_exit_tb(NULL, 0);
}
@@ -8672,7 +8671,7 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase,
CPUState *cs)
}
/* else CPU_SINGLE_STEP... */
if (nip <= 0x100 || nip > 0xf00) {
- gen_exception(ctx, gen_prep_dbgex(ctx));
+ gen_helper_raise_exception(cpu_env,
tcg_constant_i32(gen_prep_dbgex(ctx)));
return;
}
}
--
2.31.1
- [PULL 27/42] target/ppc: powerpc_excp: Consolidade TLB miss code, (continued)
- [PULL 27/42] target/ppc: powerpc_excp: Consolidade TLB miss code, David Gibson, 2021/06/03
- [PULL 30/42] target/ppc: Add infrastructure for prefixed insns, David Gibson, 2021/06/03
- [PULL 29/42] target/ppc: Move page crossing check to ppc_tr_translate_insn, David Gibson, 2021/06/03
- [PULL 34/42] target/ppc: Implement prefixed integer load instructions, David Gibson, 2021/06/03
- [PULL 33/42] target/ppc: Move D/DS/X-form integer loads to decodetree, David Gibson, 2021/06/03
- [PULL 37/42] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions, David Gibson, 2021/06/03
- [PULL 35/42] target/ppc: Move D/DS/X-form integer stores to decodetree, David Gibson, 2021/06/03
- [PULL 40/42] target/ppc: Move addpcis to decodetree, David Gibson, 2021/06/03
- [PULL 38/42] target/ppc: Implement cfuged instruction, David Gibson, 2021/06/03
- [PULL 39/42] target/ppc: Implement vcfuged instruction, David Gibson, 2021/06/03
- [PULL 42/42] target/ppc: fix single-step exception regression,
David Gibson <=
- [PULL 41/42] target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree, David Gibson, 2021/06/03
- Re: [PULL 00/42] ppc-for-6.1 queue 20210603, no-reply, 2021/06/03
- Re: [PULL 00/42] ppc-for-6.1 queue 20210603, Peter Maydell, 2021/06/03