[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v16 50/99] target/arm: fix style of arm_cpu_do_interrupt function
From: |
Alex Bennée |
Subject: |
[PATCH v16 50/99] target/arm: fix style of arm_cpu_do_interrupt functions before move |
Date: |
Fri, 4 Jun 2021 16:52:23 +0100 |
From: Claudio Fontana <cfontana@suse.de>
before refactoring the exception code, fix the style of the
functions being moved.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
target/arm/tcg/helper.c | 17 +++++++++++------
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c
index 7a9eaec5cb..5b32329895 100644
--- a/target/arm/tcg/helper.c
+++ b/target/arm/tcg/helper.c
@@ -896,10 +896,11 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
new_mode = ARM_CPU_MODE_UND;
addr = 0x04;
mask = CPSR_I;
- if (env->thumb)
+ if (env->thumb) {
offset = 2;
- else
+ } else {
offset = 4;
+ }
break;
case EXCP_SWI:
new_mode = ARM_CPU_MODE_SVC;
@@ -985,7 +986,8 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
/* High vectors. When enabled, base address cannot be remapped. */
addr += 0xffff0000;
} else {
- /* ARM v7 architectures provide a vector base address register to remap
+ /*
+ * ARM v7 architectures provide a vector base address register to remap
* the interrupt vector table.
* This register is only followed in non-monitor mode, and is banked.
* Note: only bits 31:5 are valid.
@@ -1094,7 +1096,8 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
aarch64_sve_change_el(env, cur_el, new_el, is_a64(env));
if (cur_el < new_el) {
- /* Entry vector offset depends on whether the implemented EL
+ /*
+ * Entry vector offset depends on whether the implemented EL
* immediately lower than the target level is using AArch32 or AArch64
*/
bool is_aa64;
@@ -1285,7 +1288,8 @@ static void handle_semihosting(CPUState *cs)
}
#endif
-/* Handle a CPU exception for A and R profile CPUs.
+/*
+ * Handle a CPU exception for A and R profile CPUs.
* Do any appropriate logging, handle PSCI calls, and then hand off
* to the AArch64-entry or AArch32-entry function depending on the
* target exception level's register width.
@@ -1330,7 +1334,8 @@ void arm_cpu_do_interrupt(CPUState *cs)
}
#endif
- /* Hooks may change global state so BQL should be held, also the
+ /*
+ * Hooks may change global state so BQL should be held, also the
* BQL needs to be held for any modification of
* cs->interrupt_request.
*/
--
2.20.1
- [PATCH v16 81/99] target/arm: tcg-sve: rename the narrow_vq and change_el functions, (continued)
- [PATCH v16 81/99] target/arm: tcg-sve: rename the narrow_vq and change_el functions, Alex Bennée, 2021/06/04
- [PATCH v16 66/99] tests: do not run qom-test on all machines for ARM KVM-only, Alex Bennée, 2021/06/04
- [PATCH v16 65/99] tests: device-introspect-test: cope with ARM TCG-only devices, Alex Bennée, 2021/06/04
- [PATCH v16 14/99] accel: add cpu_reset, Alex Bennée, 2021/06/04
- [PATCH v16 74/99] target/arm: cpu-sve: make cpu_sve_finalize_features return bool, Alex Bennée, 2021/06/04
- [PATCH v16 15/99] target/arm: move translate modules to tcg/, Alex Bennée, 2021/06/04
- [PATCH v16 50/99] target/arm: fix style of arm_cpu_do_interrupt functions before move,
Alex Bennée <=
- [PATCH v16 54/99] target/arm: move TCGCPUOps to tcg/tcg-cpu.c, Alex Bennée, 2021/06/04
- [PATCH v16 63/99] tests/qtest: skip bios-tables-test test_acpi_oem_fields_virt for KVM, Alex Bennée, 2021/06/04
- [PATCH v16 95/99] hw/arm: add dependency on OR_IRQ for XLNX_VERSAL, Alex Bennée, 2021/06/04
- [PATCH v16 45/99] target/arm: move sve_exception_el out of TCG helpers, Alex Bennée, 2021/06/04
- [PATCH v16 72/99] target/arm: cpu-sve: rename functions according to module prefix, Alex Bennée, 2021/06/04