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[PATCH 21/55] target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR
From: |
Peter Maydell |
Subject: |
[PATCH 21/55] target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR |
Date: |
Mon, 7 Jun 2021 17:57:47 +0100 |
Implement the MVE vector logical operations operating
on two registers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper-mve.h | 6 ++++++
target/arm/mve.decode | 9 +++++++++
target/arm/mve_helper.c | 28 ++++++++++++++++++++++++++
target/arm/translate-mve.c | 41 ++++++++++++++++++++++++++++++++++++++
4 files changed, 84 insertions(+)
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index ece9c481367..ad09170c9cf 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -65,3 +65,9 @@ DEF_HELPER_FLAGS_3(mve_vnegh, TCG_CALL_NO_WG, void, env, ptr,
ptr)
DEF_HELPER_FLAGS_3(mve_vnegw, TCG_CALL_NO_WG, void, env, ptr, ptr)
DEF_HELPER_FLAGS_3(mve_vfnegh, TCG_CALL_NO_WG, void, env, ptr, ptr)
DEF_HELPER_FLAGS_3(mve_vfnegs, TCG_CALL_NO_WG, void, env, ptr, ptr)
+
+DEF_HELPER_FLAGS_4(mve_vand, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vbic, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vorr, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vorn, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_veor, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index 09849917f5a..332e0b8d1d6 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -25,6 +25,7 @@
&vldr_vstr rn qd imm p a w size l u
&1op qd qm size
+&2op qd qm qn size
@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
# Note that both Rn and Qd are 3 bits only (no D bit)
@@ -32,6 +33,7 @@
@1op .... .... .... size:2 .. .... .... .... .... &1op qd=%qd qm=%qm
@1op_nosz .... .... .... .... .... .... .... .... &1op qd=%qd qm=%qm size=0
+@2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn
size=0
# Vector loads and stores
@@ -68,6 +70,13 @@ VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111101
....... @vldr_vstr \
VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111110 ....... @vldr_vstr \
size=2 p=1
+# Vector 2-op
+VAND 1110 1111 0 . 00 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz
+VBIC 1110 1111 0 . 01 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz
+VORR 1110 1111 0 . 10 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz
+VORN 1110 1111 0 . 11 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz
+VEOR 1111 1111 0 . 00 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz
+
# Vector miscellaneous
VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index a5ed4e01e33..6b3d4dbf2da 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -306,3 +306,31 @@ DO_1OP(vnegw, 4, int32_t, H4, DO_NEG)
DO_1OP(vfnegh, 2, uint16_t, H2, DO_FNEG)
DO_1OP(vfnegs, 4, uint32_t, H4, DO_FNEG)
+
+#define DO_2OP(OP, ESIZE, TYPE, H, FN) \
+ void HELPER(glue(mve_, OP))(CPUARMState *env, \
+ void *vd, void *vn, void *vm) \
+ { \
+ TYPE *d = vd, *n = vn, *m = vm; \
+ uint16_t mask = mve_element_mask(env); \
+ unsigned e; \
+ for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \
+ TYPE r = FN(n[H(e)], m[H(e)]); \
+ uint64_t bytemask = mask_to_bytemask##ESIZE(mask); \
+ d[H(e)] &= ~bytemask; \
+ d[H(e)] |= (r & bytemask); \
+ } \
+ mve_advance_vpt(env); \
+ }
+
+#define DO_AND(N, M) ((N) & (M))
+#define DO_BIC(N, M) ((N) & ~(M))
+#define DO_ORR(N, M) ((N) | (M))
+#define DO_ORN(N, M) ((N) | ~(M))
+#define DO_EOR(N, M) ((N) ^ (M))
+
+DO_2OP(vand, 1, uint8_t, H1, DO_AND)
+DO_2OP(vbic, 1, uint8_t, H1, DO_BIC)
+DO_2OP(vorr, 1, uint8_t, H1, DO_ORR)
+DO_2OP(vorn, 1, uint8_t, H1, DO_ORN)
+DO_2OP(veor, 1, uint8_t, H1, DO_EOR)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index b4fc4054fe1..0e0fa252364 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -30,6 +30,7 @@
typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
+typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr);
/* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */
static inline long mve_qreg_offset(unsigned reg)
@@ -322,3 +323,43 @@ static bool trans_VNEG_fp(DisasContext *s, arg_1op *a)
}
return do_1op(s, a, fns[a->size]);
}
+
+static bool do_2op(DisasContext *s, arg_2op *a, MVEGenTwoOpFn fn)
+{
+ TCGv_ptr qd, qn, qm;
+
+ if (!dc_isar_feature(aa32_mve, s)) {
+ return false;
+ }
+ if (a->qd > 7 || a->qn > 7 || a->qm > 7 || !fn) {
+ return false;
+ }
+ if (!mve_eci_check(s)) {
+ return true;
+ }
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ qd = mve_qreg_ptr(a->qd);
+ qn = mve_qreg_ptr(a->qn);
+ qm = mve_qreg_ptr(a->qm);
+ fn(cpu_env, qd, qn, qm);
+ tcg_temp_free_ptr(qd);
+ tcg_temp_free_ptr(qn);
+ tcg_temp_free_ptr(qm);
+ mve_update_eci(s);
+ return true;
+}
+
+#define DO_LOGIC(INSN, HELPER) \
+ static bool trans_##INSN(DisasContext *s, arg_2op *a) \
+ { \
+ return do_2op(s, a, HELPER); \
+ }
+
+DO_LOGIC(VAND, gen_helper_mve_vand)
+DO_LOGIC(VBIC, gen_helper_mve_vbic)
+DO_LOGIC(VORR, gen_helper_mve_vorr)
+DO_LOGIC(VORN, gen_helper_mve_vorn)
+DO_LOGIC(VEOR, gen_helper_mve_veor)
--
2.20.1
- Re: [PATCH 11/55] target/arm: Implement MVE VLDR/VSTR (non-widening forms), (continued)
- [PATCH 12/55] target/arm: Implement widening/narrowing MVE VLDR/VSTR insns, Peter Maydell, 2021/06/07
- [PATCH 14/55] target/arm: Implement MVE VCLS, Peter Maydell, 2021/06/07
- [PATCH 21/55] target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR,
Peter Maydell <=
- [PATCH 20/55] target/arm: Implement MVE VDUP, Peter Maydell, 2021/06/07
[PATCH 32/55] target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH, Peter Maydell, 2021/06/07
[PATCH 18/55] target/arm: Implement MVE VABS, Peter Maydell, 2021/06/07