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[PATCH 37/55] target/arm: Implement MVE VPST
From: |
Peter Maydell |
Subject: |
[PATCH 37/55] target/arm: Implement MVE VPST |
Date: |
Mon, 7 Jun 2021 17:58:03 +0100 |
Implement the MVE VPST insn, which sets the predicate mask
fields in the VPR to the immediate value encoded in the insn.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/mve.decode | 4 +++
target/arm/translate-mve.c | 59 ++++++++++++++++++++++++++++++++++++++
2 files changed, 63 insertions(+)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index a3dbdb72a5c..e189e2de648 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -168,3 +168,7 @@ VHADD_U_scalar 1111 1110 0 . .. ... 0 ... 0 1111 . 100
.... @2scalar
VHSUB_S_scalar 1110 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar
VHSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar
VBRSR 1111 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar
+
+# Predicate operations
+%mask_22_13 22:1 13:3
+VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index b7bf7d0960f..45a71a22853 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -588,3 +588,62 @@ static bool trans_VRMLSLDAVH(DisasContext *s, arg_vmlaldav
*a)
};
return do_long_dual_acc(s, a, fns[a->x]);
}
+
+static bool trans_VPST(DisasContext *s, arg_VPST *a)
+{
+ TCGv_i32 vpr, mask;
+
+ /* mask == 0 is a "related encoding" */
+ if (!dc_isar_feature(aa32_mve, s) || !a->mask) {
+ return false;
+ }
+ if (!mve_eci_check(s)) {
+ return true;
+ }
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+ /*
+ * Set the VPR mask fields. We take advantage of MASK01 and MASK23
+ * being adjacent fields in the register.
+ *
+ * This insn is not predicated, but it is subject to beat-wise
+ * execution, and the mask is updated on the odd-numbered beats.
+ * So if PSR.ECI says we should skip beat 1, we mustn't update the
+ * 01 mask field.
+ */
+ vpr = load_cpu_field(v7m.vpr);
+ switch (s->eci) {
+ case ECI_NONE:
+ case ECI_A0:
+ /* Update both 01 and 23 fields */
+ mask = tcg_const_i32(a->mask | (a->mask << 4));
+ tcg_gen_deposit_i32(vpr, vpr, mask, R_V7M_VPR_MASK01_SHIFT,
+ R_V7M_VPR_MASK01_LENGTH + R_V7M_VPR_MASK23_LENGTH);
+ break;
+ case ECI_A0A1:
+ case ECI_A0A1A2:
+ case ECI_A0A1A2B0:
+ /* Update only the 23 mask field */
+ mask = tcg_const_i32(a->mask);
+ tcg_gen_deposit_i32(vpr, vpr, mask, R_V7M_VPR_MASK23_SHIFT,
+ R_V7M_VPR_MASK23_LENGTH);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ store_cpu_field(vpr, v7m.vpr);
+ tcg_temp_free_i32(mask);
+
+ if (s->eci) {
+ TCGv_i32 eci;
+ mve_update_eci(s);
+ /*
+ * Update ECI in CPUState (since we didn't call a helper
+ * that will call mve_advance_vpt()).
+ */
+ eci = tcg_const_i32(s->eci << 4);
+ store_cpu_field(eci, condexec_bits);
+ }
+ return true;
+}
--
2.20.1
- [PATCH 33/55] target/arm: Implement MVE VADD (scalar), (continued)
- [PATCH 33/55] target/arm: Implement MVE VADD (scalar), Peter Maydell, 2021/06/07
- [PATCH 45/55] target/arm: Implement MVE VSHL insn, Peter Maydell, 2021/06/07
- [PATCH 46/55] target/arm: Implement MVE VRSHL, Peter Maydell, 2021/06/07
- [PATCH 51/55] target/arm: Implement MVE VADC, VSBC, Peter Maydell, 2021/06/07
- [PATCH 35/55] target/arm: Implement MVE VHADD, VHSUB (scalar), Peter Maydell, 2021/06/07
- [PATCH 37/55] target/arm: Implement MVE VPST,
Peter Maydell <=
- [PATCH 29/55] target/arm: Implement MVE VMLALDAV, Peter Maydell, 2021/06/07
- [PATCH 27/55] target/arm: Implement MVE VHADD, VHSUB, Peter Maydell, 2021/06/07
- [PATCH 43/55] target/arm: Implement MVE VQSHL (vector), Peter Maydell, 2021/06/07
- [PATCH 54/55] target/arm: Implement MVE VADDV, Peter Maydell, 2021/06/07