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[PULL 29/32] target/riscv: rvb: address calculation
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From: |
Alistair Francis |
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Subject: |
[PULL 29/32] target/riscv: rvb: address calculation |
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Date: |
Tue, 8 Jun 2021 10:29:44 +1000 |
From: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210505160620.15723-15-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn32.decode | 6 +++++
target/riscv/translate.c | 32 +++++++++++++++++++++++++
target/riscv/insn_trans/trans_rvb.c.inc | 24 +++++++++++++++++++
3 files changed, 62 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e6dab8dbbc..287920ee9b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -686,6 +686,9 @@ ror 0110000 .......... 101 ..... 0110011 @r
rol 0110000 .......... 001 ..... 0110011 @r
grev 0110100 .......... 101 ..... 0110011 @r
gorc 0010100 .......... 101 ..... 0110011 @r
+sh1add 0010000 .......... 010 ..... 0110011 @r
+sh2add 0010000 .......... 100 ..... 0110011 @r
+sh3add 0010000 .......... 110 ..... 0110011 @r
bseti 00101. ........... 001 ..... 0010011 @sh
bclri 01001. ........... 001 ..... 0010011 @sh
@@ -714,6 +717,9 @@ rorw 0110000 .......... 101 ..... 0111011 @r
rolw 0110000 .......... 001 ..... 0111011 @r
grevw 0110100 .......... 101 ..... 0111011 @r
gorcw 0010100 .......... 101 ..... 0111011 @r
+sh1add_uw 0010000 .......... 010 ..... 0111011 @r
+sh2add_uw 0010000 .......... 100 ..... 0111011 @r
+sh3add_uw 0010000 .......... 110 ..... 0111011 @r
bsetiw 0010100 .......... 001 ..... 0011011 @sh5
bclriw 0100100 .......... 001 ..... 0011011 @sh5
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 35d4d36eef..ae9b5f7a2e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -649,6 +649,21 @@ static bool gen_grevi(DisasContext *ctx, arg_grevi *a)
return true;
}
+#define GEN_SHADD(SHAMT) \
+static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
+{ \
+ TCGv t = tcg_temp_new(); \
+ \
+ tcg_gen_shli_tl(t, arg1, SHAMT); \
+ tcg_gen_add_tl(ret, t, arg2); \
+ \
+ tcg_temp_free(t); \
+}
+
+GEN_SHADD(1)
+GEN_SHADD(2)
+GEN_SHADD(3)
+
static void gen_ctzw(TCGv ret, TCGv arg1)
{
tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
@@ -733,6 +748,23 @@ static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2)
gen_helper_gorcw(ret, arg1, arg2);
}
+#define GEN_SHADD_UW(SHAMT) \
+static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
+{ \
+ TCGv t = tcg_temp_new(); \
+ \
+ tcg_gen_ext32u_tl(t, arg1); \
+ \
+ tcg_gen_shli_tl(t, t, SHAMT); \
+ tcg_gen_add_tl(ret, t, arg2); \
+ \
+ tcg_temp_free(t); \
+}
+
+GEN_SHADD_UW(1)
+GEN_SHADD_UW(2)
+GEN_SHADD_UW(3)
+
static bool gen_arith(DisasContext *ctx, arg_r *a,
void(*func)(TCGv, TCGv, TCGv))
{
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index ec9f9d2ef2..b27114a068 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -226,6 +226,17 @@ static bool trans_gorci(DisasContext *ctx, arg_gorci *a)
return gen_shifti(ctx, a, gen_helper_gorc);
}
+#define GEN_TRANS_SHADD(SHAMT) \
+static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
+{ \
+ REQUIRE_EXT(ctx, RVB); \
+ return gen_arith(ctx, a, gen_sh##SHAMT##add); \
+}
+
+GEN_TRANS_SHADD(1)
+GEN_TRANS_SHADD(2)
+GEN_TRANS_SHADD(3)
+
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
@@ -386,3 +397,16 @@ static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a)
REQUIRE_EXT(ctx, RVB);
return gen_shiftiw(ctx, a, gen_gorcw);
}
+
+#define GEN_TRANS_SHADD_UW(SHAMT) \
+static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, \
+ arg_sh##SHAMT##add_uw *a) \
+{ \
+ REQUIRE_64BIT(ctx); \
+ REQUIRE_EXT(ctx, RVB); \
+ return gen_arith(ctx, a, gen_sh##SHAMT##add_uw); \
+}
+
+GEN_TRANS_SHADD_UW(1)
+GEN_TRANS_SHADD_UW(2)
+GEN_TRANS_SHADD_UW(3)
--
2.31.1
- [PULL 19/32] target/riscv: rvb: logic-with-negate, (continued)
- [PULL 19/32] target/riscv: rvb: logic-with-negate, Alistair Francis, 2021/06/07
- [PULL 20/32] target/riscv: rvb: pack two words into one register, Alistair Francis, 2021/06/07
- [PULL 21/32] target/riscv: rvb: min/max instructions, Alistair Francis, 2021/06/07
- [PULL 22/32] target/riscv: rvb: sign-extend instructions, Alistair Francis, 2021/06/07
- [PULL 23/32] target/riscv: add gen_shifti() and gen_shiftiw() helper functions, Alistair Francis, 2021/06/07
- [PULL 24/32] target/riscv: rvb: single-bit instructions, Alistair Francis, 2021/06/07
- [PULL 25/32] target/riscv: rvb: shift ones, Alistair Francis, 2021/06/07
- [PULL 26/32] target/riscv: rvb: rotate (left/right), Alistair Francis, 2021/06/07
- [PULL 27/32] target/riscv: rvb: generalized reverse, Alistair Francis, 2021/06/07
- [PULL 28/32] target/riscv: rvb: generalized or-combine, Alistair Francis, 2021/06/07
- [PULL 29/32] target/riscv: rvb: address calculation,
Alistair Francis <=
- [PULL 30/32] target/riscv: rvb: add/shift with prefix zero-extend, Alistair Francis, 2021/06/07
- [PULL 31/32] target/riscv: rvb: support and turn on B-extension from command line, Alistair Francis, 2021/06/07
- [PULL 32/32] target/riscv: rvb: add b-ext version cpu option, Alistair Francis, 2021/06/07
- Re: [PULL 00/32] riscv-to-apply queue, Peter Maydell, 2021/06/08