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[PATCH v2 23/37] target/riscv: Signed 16-bit Multiply with 64-bit Add/Su
From: |
LIU Zhiwei |
Subject: |
[PATCH v2 23/37] target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract Instructions |
Date: |
Thu, 10 Jun 2021 15:58:54 +0800 |
one or two 16x16 multiply as operands for an add/subtract operation with
another 64-bit operand.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/helper.h | 11 ++
target/riscv/insn32.decode | 11 ++
target/riscv/insn_trans/trans_rvp.c.inc | 12 ++
target/riscv/packed_helper.c | 151 ++++++++++++++++++++++++
4 files changed, 185 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index c3c086bed0..87a0779842 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1350,3 +1350,14 @@ DEF_HELPER_4(kmar64, i64, env, tl, tl, i64)
DEF_HELPER_4(kmsr64, i64, env, tl, tl, i64)
DEF_HELPER_4(ukmar64, i64, env, tl, tl, i64)
DEF_HELPER_4(ukmsr64, i64, env, tl, tl, i64)
+
+DEF_HELPER_4(smalbb, i64, env, tl, tl, i64)
+DEF_HELPER_4(smalbt, i64, env, tl, tl, i64)
+DEF_HELPER_4(smaltt, i64, env, tl, tl, i64)
+DEF_HELPER_4(smalda, i64, env, tl, tl, i64)
+DEF_HELPER_4(smalxda, i64, env, tl, tl, i64)
+DEF_HELPER_4(smalds, i64, env, tl, tl, i64)
+DEF_HELPER_4(smalxds, i64, env, tl, tl, i64)
+DEF_HELPER_4(smaldrs, i64, env, tl, tl, i64)
+DEF_HELPER_4(smslda, i64, env, tl, tl, i64)
+DEF_HELPER_4(smslxda, i64, env, tl, tl, i64)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 5d123bbb97..d1668b34cb 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -953,3 +953,14 @@ kmar64 1001010 ..... ..... 001 ..... 1110111 @r
kmsr64 1001011 ..... ..... 001 ..... 1110111 @r
ukmar64 1011010 ..... ..... 001 ..... 1110111 @r
ukmsr64 1011011 ..... ..... 001 ..... 1110111 @r
+
+smalbb 1000100 ..... ..... 001 ..... 1110111 @r
+smalbt 1001100 ..... ..... 001 ..... 1110111 @r
+smaltt 1010100 ..... ..... 001 ..... 1110111 @r
+smalda 1000110 ..... ..... 001 ..... 1110111 @r
+smalxda 1001110 ..... ..... 001 ..... 1110111 @r
+smalds 1000101 ..... ..... 001 ..... 1110111 @r
+smaldrs 1001101 ..... ..... 001 ..... 1110111 @r
+smalxds 1010101 ..... ..... 001 ..... 1110111 @r
+smslda 1010110 ..... ..... 001 ..... 1110111 @r
+smslxda 1011110 ..... ..... 001 ..... 1110111 @r
diff --git a/target/riscv/insn_trans/trans_rvp.c.inc
b/target/riscv/insn_trans/trans_rvp.c.inc
index 63b6810227..7c91bdc888 100644
--- a/target/riscv/insn_trans/trans_rvp.c.inc
+++ b/target/riscv/insn_trans/trans_rvp.c.inc
@@ -657,3 +657,15 @@ GEN_RVP_R_D64_ACC_OOL(kmar64);
GEN_RVP_R_D64_ACC_OOL(kmsr64);
GEN_RVP_R_D64_ACC_OOL(ukmar64);
GEN_RVP_R_D64_ACC_OOL(ukmsr64);
+
+/* Signed 16-bit Multiply with 64-bit Add/Subtract Instructions */
+GEN_RVP_R_D64_ACC_OOL(smalbb);
+GEN_RVP_R_D64_ACC_OOL(smalbt);
+GEN_RVP_R_D64_ACC_OOL(smaltt);
+GEN_RVP_R_D64_ACC_OOL(smalda);
+GEN_RVP_R_D64_ACC_OOL(smalxda);
+GEN_RVP_R_D64_ACC_OOL(smalds);
+GEN_RVP_R_D64_ACC_OOL(smaldrs);
+GEN_RVP_R_D64_ACC_OOL(smalxds);
+GEN_RVP_R_D64_ACC_OOL(smslda);
+GEN_RVP_R_D64_ACC_OOL(smslxda);
diff --git a/target/riscv/packed_helper.c b/target/riscv/packed_helper.c
index 59a06c604d..3330a2ecec 100644
--- a/target/riscv/packed_helper.c
+++ b/target/riscv/packed_helper.c
@@ -2375,3 +2375,154 @@ static inline void do_ukmsr64(CPURISCVState *env, void
*vd, void *va,
}
RVPR64_ACC(ukmsr64, 1, 4);
+
+/* Signed 16-bit Multiply with 64-bit Add/Subtract Instructions */
+static inline void do_smalbb(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int64_t *d = vd, *c = vc;
+ int16_t *a = va, *b = vb;
+
+ if (i == 0) {
+ *d = *c;
+ }
+
+ *d += (int64_t)a[H2(i)] * b[H2(i)];
+}
+
+RVPR64_ACC(smalbb, 2, 2);
+
+static inline void do_smalbt(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int64_t *d = vd, *c = vc;
+ int16_t *a = va, *b = vb;
+
+ if (i == 0) {
+ *d = *c;
+ }
+
+ *d += (int64_t)a[H2(i)] * b[H2(i + 1)];
+}
+
+RVPR64_ACC(smalbt, 2, 2);
+
+static inline void do_smaltt(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int64_t *d = vd, *c = vc;
+ int16_t *a = va, *b = vb;
+
+ if (i == 0) {
+ *d = *c;
+ }
+
+ *d += (int64_t)a[H2(i + 1)] * b[H2(i + 1)];
+}
+
+RVPR64_ACC(smaltt, 2, 2);
+
+static inline void do_smalda(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int64_t *d = vd, *c = vc;
+ int16_t *a = va, *b = vb;
+
+ if (i == 0) {
+ *d = *c;
+ }
+
+ *d += (int64_t)a[H2(i)] * b[H2(i)] + (int64_t)a[H2(i + 1)] * b[H2(i + 1)];
+}
+
+RVPR64_ACC(smalda, 2, 2);
+
+static inline void do_smalxda(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int64_t *d = vd, *c = vc;
+ int16_t *a = va, *b = vb;
+
+ if (i == 0) {
+ *d = *c;
+ }
+
+ *d += (int64_t)a[H2(i)] * b[H2(i + 1)] + (int64_t)a[H2(i + 1)] * b[H2(i)];
+}
+
+RVPR64_ACC(smalxda, 2, 2);
+
+static inline void do_smalds(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int64_t *d = vd, *c = vc;
+ int16_t *a = va, *b = vb;
+
+ if (i == 0) {
+ *d = *c;
+ }
+
+ *d += (int64_t)a[H2(i + 1)] * b[H2(i + 1)] - (int64_t)a[H2(i)] * b[H2(i)];
+}
+
+RVPR64_ACC(smalds, 2, 2);
+
+static inline void do_smaldrs(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int64_t *d = vd, *c = vc;
+ int16_t *a = va, *b = vb;
+
+ if (i == 0) {
+ *d = *c;
+ }
+
+ *d += (int64_t)a[H2(i)] * b[H2(i)] - (int64_t)a[H2(i + 1)] * b[H2(i + 1)];
+}
+
+RVPR64_ACC(smaldrs, 2, 2);
+
+static inline void do_smalxds(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int64_t *d = vd, *c = vc;
+ int16_t *a = va, *b = vb;
+
+ if (i == 0) {
+ *d = *c;
+ }
+
+ *d += (int64_t)a[H2(i + 1)] * b[H2(i)] - (int64_t)a[H2(i)] * b[H2(i + 1)];
+}
+
+RVPR64_ACC(smalxds, 2, 2);
+
+static inline void do_smslda(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int64_t *d = vd, *c = vc;
+ int16_t *a = va, *b = vb;
+
+ if (i == 0) {
+ *d = *c;
+ }
+
+ *d -= (int64_t)a[H2(i)] * b[H2(i)] + (int64_t)a[H2(i + 1)] * b[H2(i + 1)];
+}
+
+RVPR64_ACC(smslda, 2, 2);
+
+static inline void do_smslxda(CPURISCVState *env, void *vd, void *va,
+ void *vb, void *vc, uint8_t i)
+{
+ int64_t *d = vd, *c = vc;
+ int16_t *a = va, *b = vb;
+
+ if (i == 0) {
+ *d = *c;
+ }
+
+ *d -= (int64_t)a[H2(i + 1)] * b[H2(i)] + (int64_t)a[H2(i)] * b[H2(i + 1)];
+}
+
+RVPR64_ACC(smslxda, 2, 2);
--
2.25.1
- [PATCH v2 13/37] target/riscv: 8-bit Unpacking Instructions, (continued)
- [PATCH v2 13/37] target/riscv: 8-bit Unpacking Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 14/37] target/riscv: 16-bit Packing Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 16/37] target/riscv: Signed MSW 32x16 Multiply and Add Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 18/37] target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 19/37] target/riscv: Partial-SIMD Miscellaneous Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 20/37] target/riscv: 8-bit Multiply with 32-bit Add Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 21/37] target/riscv: 64-bit Add/Subtract Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 22/37] target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 23/37] target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract Instructions,
LIU Zhiwei <=
- [PATCH v2 24/37] target/riscv: Non-SIMD Q15 saturation ALU Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 25/37] target/riscv: Non-SIMD Q31 saturation ALU Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 26/37] target/riscv: 32-bit Computation Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 27/37] target/riscv: Non-SIMD Miscellaneous Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 29/37] target/riscv: RV64 Only SIMD 32-bit Shift Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 32/37] target/riscv: RV64 Only 32-bit Multiply Instructions, LIU Zhiwei, 2021/06/10
- [PATCH v2 33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions, LIU Zhiwei, 2021/06/10