Re: [PATCH 20/28] target/arm: Improve REV32

[Philippe Mathieu-Daudé]

On 6/14/21 10:37 AM, Richard Henderson wrote:
> For the sf version, we are performing two 32-bit bswaps
> in either half of the register.  This is equivalent to
> performing one 64-bit bswap followed by a rotate.
> 
> For the non-sf version, we can remove TCG_BSWAP_IZ
> and the preceding zero-extension.
> 
> Cc: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/translate-a64.c | 17 ++++-------------
>  1 file changed, 4 insertions(+), 13 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>