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[PULL 37/45] target/i386: Added Intercept CR0 writes check
From: |
Paolo Bonzini |
Subject: |
[PULL 37/45] target/i386: Added Intercept CR0 writes check |
Date: |
Thu, 17 Jun 2021 11:31:26 +0200 |
From: Lara Lazier <laramglazier@gmail.com>
When the selective CR0 write intercept is set, all writes to bits in
CR0 other than CR0.TS or CR0.MP cause a VMEXIT.
Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Message-Id: <20210616123907.17765-5-laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/sysemu/misc_helper.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/target/i386/tcg/sysemu/misc_helper.c
b/target/i386/tcg/sysemu/misc_helper.c
index 0cef2f1a4c..db0d8a9d79 100644
--- a/target/i386/tcg/sysemu/misc_helper.c
+++ b/target/i386/tcg/sysemu/misc_helper.c
@@ -84,6 +84,15 @@ void helper_write_crN(CPUX86State *env, int reg,
target_ulong t0)
{
switch (reg) {
case 0:
+ /*
+ * If we reach this point, the CR0 write intercept is disabled.
+ * But we could still exit if the hypervisor has requested the selective
+ * intercept for bits other than TS and MP
+ */
+ if (cpu_svm_has_intercept(env, SVM_EXIT_CR0_SEL_WRITE) &&
+ ((env->cr[0] ^ t0) & ~(CR0_TS_MASK | CR0_MP_MASK))) {
+ cpu_vmexit(env, SVM_EXIT_CR0_SEL_WRITE, 0, GETPC());
+ }
cpu_x86_update_cr0(env, t0);
break;
case 3:
--
2.31.1
- [PULL 20/45] util/mmap-alloc: Factor out activating of memory to mmap_activate(), (continued)
- [PULL 20/45] util/mmap-alloc: Factor out activating of memory to mmap_activate(), Paolo Bonzini, 2021/06/17
- [PULL 22/45] softmmu/memory: Pass ram_flags to memory_region_init_ram_shared_nomigrate(), Paolo Bonzini, 2021/06/17
- [PULL 26/45] util/mmap-alloc: Support RAM_NORESERVE via MAP_NORESERVE under Linux, Paolo Bonzini, 2021/06/17
- [PULL 23/45] softmmu/memory: Pass ram_flags to qemu_ram_alloc() and qemu_ram_alloc_internal(), Paolo Bonzini, 2021/06/17
- [PULL 29/45] qmp: Include "share" property of memory backends, Paolo Bonzini, 2021/06/17
- [PULL 33/45] configure: map x32 to cpu_family x86_64 for meson, Paolo Bonzini, 2021/06/17
- [PULL 36/45] target/i386: Added consistency checks for CR0, Paolo Bonzini, 2021/06/17
- [PULL 38/45] configure: Use -std=gnu11, Paolo Bonzini, 2021/06/17
- [PULL 40/45] util: Use real functions for thread-posix QemuRecMutex, Paolo Bonzini, 2021/06/17
- [PULL 42/45] util: Use unique type for QemuRecMutex in thread-posix.h, Paolo Bonzini, 2021/06/17
- [PULL 37/45] target/i386: Added Intercept CR0 writes check,
Paolo Bonzini <=
- [PULL 44/45] qemu/compiler: Remove QEMU_GENERIC, Paolo Bonzini, 2021/06/17
- [PULL 43/45] include/qemu/lockable: Use _Generic instead of QEMU_GENERIC, Paolo Bonzini, 2021/06/17
- [PULL 21/45] softmmu/memory: Pass ram_flags to qemu_ram_alloc_from_fd(), Paolo Bonzini, 2021/06/17
- [PULL 25/45] memory: Introduce RAM_NORESERVE and wire it up in qemu_ram_mmap(), Paolo Bonzini, 2021/06/17
- [PULL 24/45] util/mmap-alloc: Pass flags instead of separate bools to qemu_ram_mmap(), Paolo Bonzini, 2021/06/17
- [PULL 27/45] hostmem: Wire up RAM_NORESERVE via "reserve" property, Paolo Bonzini, 2021/06/17
- [PULL 28/45] qmp: Clarify memory backend properties returned via query-memdev, Paolo Bonzini, 2021/06/17
- [PULL 30/45] hmp: Print "share" property of memory backends with "info memdev", Paolo Bonzini, 2021/06/17
- [PULL 35/45] target/i386: Added consistency checks for VMRUN intercept and ASID, Paolo Bonzini, 2021/06/17
- [PULL 34/45] target/i386: Refactored intercept checks into cpu_svm_has_intercept, Paolo Bonzini, 2021/06/17