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Re: [PATCH] target/ppc/spapr: Update H_GET_CPU_CHARACTERISTICS L1D cache
From: |
David Gibson |
Subject: |
Re: [PATCH] target/ppc/spapr: Update H_GET_CPU_CHARACTERISTICS L1D cache flush bits |
Date: |
Sat, 19 Jun 2021 19:26:39 +1000 |
On Tue, Jun 15, 2021 at 02:41:07PM +1000, Nicholas Piggin wrote:
> There are several new L1D cache flush bits added to the hcall which reflect
> hardware security features for speculative cache access issues.
>
> These behaviours are now being specified as negative in order to simplify
> patched kernel compatibility with older firmware (a new problem found in
> existing systems would automatically be vulnerable).
I don't really understand all the consequences of that. What I need
to know here, is if it's safe to unconditionally enable these bits,
even for older machine types.
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> hw/ppc/spapr_hcall.c | 2 ++
> include/hw/ppc/spapr.h | 3 +++
> 2 files changed, 5 insertions(+)
>
> diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
> index f25014afda..dfd9df469d 100644
> --- a/hw/ppc/spapr_hcall.c
> +++ b/hw/ppc/spapr_hcall.c
> @@ -1299,6 +1299,8 @@ static target_ulong
> h_get_cpu_characteristics(PowerPCCPU *cpu,
> behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR;
> break;
> case SPAPR_CAP_FIXED:
> + behaviour |= H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY;
> + behaviour |= H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS;
> break;
> default: /* broken */
> assert(safe_cache == SPAPR_CAP_BROKEN);
> diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
> index f05219f75e..0f25d081a8 100644
> --- a/include/hw/ppc/spapr.h
> +++ b/include/hw/ppc/spapr.h
> @@ -398,10 +398,13 @@ struct SpaprMachineState {
> #define H_CPU_CHAR_THR_RECONF_TRIG PPC_BIT(6)
> #define H_CPU_CHAR_CACHE_COUNT_DIS PPC_BIT(7)
> #define H_CPU_CHAR_BCCTR_FLUSH_ASSIST PPC_BIT(9)
> +
> #define H_CPU_BEHAV_FAVOUR_SECURITY PPC_BIT(0)
> #define H_CPU_BEHAV_L1D_FLUSH_PR PPC_BIT(1)
> #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR PPC_BIT(2)
> #define H_CPU_BEHAV_FLUSH_COUNT_CACHE PPC_BIT(5)
> +#define H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY PPC_BIT(7)
> +#define H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS PPC_BIT(8)
>
> /* Each control block has to be on a 4K boundary */
> #define H_CB_ALIGNMENT 4096
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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