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[PULL 18/37] s390x/tcg: Implement 64 bit for VECTOR FP LOAD LENGTHENED
From: |
Cornelia Huck |
Subject: |
[PULL 18/37] s390x/tcg: Implement 64 bit for VECTOR FP LOAD LENGTHENED |
Date: |
Mon, 21 Jun 2021 11:58:23 +0200 |
From: David Hildenbrand <david@redhat.com>
64 bit -> 128 bit, there is only a single final element.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20210608092337.12221-18-david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
target/s390x/helper.h | 1 +
target/s390x/translate_vx.c.inc | 19 ++++++++++++++++---
target/s390x/vec_fpu_helper.c | 13 +++++++++++++
3 files changed, 30 insertions(+), 3 deletions(-)
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index dca436f710cd..b5ba159402b2 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -285,6 +285,7 @@ DEF_HELPER_FLAGS_4(gvec_vfi32, TCG_CALL_NO_WG, void, ptr,
cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vfi64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vfi128, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vfll32, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
+DEF_HELPER_FLAGS_4(gvec_vfll64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_4(gvec_vflr64, TCG_CALL_NO_WG, void, ptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfm32, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_vfm64, TCG_CALL_NO_WG, void, ptr, cptr, cptr, env, i32)
diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.inc
index 822a9d05134b..472afca45e25 100644
--- a/target/s390x/translate_vx.c.inc
+++ b/target/s390x/translate_vx.c.inc
@@ -2781,14 +2781,27 @@ static DisasJumpType op_vfll(DisasContext *s, DisasOps
*o)
{
const uint8_t fpf = get_field(s, m3);
const uint8_t m4 = get_field(s, m4);
+ gen_helper_gvec_2_ptr *fn = NULL;
- if (fpf != FPF_SHORT || extract32(m4, 0, 3)) {
+ switch (fpf) {
+ case FPF_SHORT:
+ fn = gen_helper_gvec_vfll32;
+ break;
+ case FPF_LONG:
+ if (s390_has_feat(S390_FEAT_VECTOR_ENH)) {
+ fn = gen_helper_gvec_vfll64;
+ }
+ break;
+ default:
+ break;
+ }
+
+ if (!fn || extract32(m4, 0, 3)) {
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
- gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env,
- m4, gen_helper_gvec_vfll32);
+ gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, m4, fn);
return DISAS_NEXT;
}
diff --git a/target/s390x/vec_fpu_helper.c b/target/s390x/vec_fpu_helper.c
index fba5261ac4c1..75e3212582bc 100644
--- a/target/s390x/vec_fpu_helper.c
+++ b/target/s390x/vec_fpu_helper.c
@@ -522,6 +522,19 @@ void HELPER(gvec_vfll32)(void *v1, const void *v2,
CPUS390XState *env,
*(S390Vector *)v1 = tmp;
}
+void HELPER(gvec_vfll64)(void *v1, const void *v2, CPUS390XState *env,
+ uint32_t desc)
+{
+ /* load from even element */
+ const float128 ret = float64_to_float128(s390_vec_read_float64(v2, 0),
+ &env->fpu_status);
+ uint8_t vxc, vec_exc = 0;
+
+ vxc = check_ieee_exc(env, 0, false, &vec_exc);
+ handle_ieee_exc(env, vxc, vec_exc, GETPC());
+ s390_vec_write_float128(v1, ret);
+}
+
void HELPER(gvec_vflr64)(void *v1, const void *v2, CPUS390XState *env,
uint32_t desc)
{
--
2.31.1
- [PULL 06/37] s390x/tcg: Simplify vfc64() handling, (continued)
- [PULL 06/37] s390x/tcg: Simplify vfc64() handling, Cornelia Huck, 2021/06/21
- [PULL 08/37] s390x/tcg: Simplify vfma64() handling, Cornelia Huck, 2021/06/21
- [PULL 10/37] s390x/tcg: Simplify vflr64() handling, Cornelia Huck, 2021/06/21
- [PULL 09/37] s390x/tcg: Simplify vfll32() handling, Cornelia Huck, 2021/06/21
- [PULL 11/37] s390x/tcg: Simplify wfc64() handling, Cornelia Huck, 2021/06/21
- [PULL 12/37] s390x/tcg: Implement VECTOR BIT PERMUTE, Cornelia Huck, 2021/06/21
- [PULL 14/37] s390x/tcg: Implement 32/128 bit for VECTOR FP (ADD|DIVIDE|MULTIPLY|SUBTRACT), Cornelia Huck, 2021/06/21
- [PULL 13/37] s390x/tcg: Implement VECTOR MULTIPLY SUM LOGICAL, Cornelia Huck, 2021/06/21
- [PULL 15/37] s390x/tcg: Implement 32/128 bit for VECTOR (LOAD FP INTEGER|FP SQUARE ROOT), Cornelia Huck, 2021/06/21
- [PULL 16/37] s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE *, Cornelia Huck, 2021/06/21
- [PULL 18/37] s390x/tcg: Implement 64 bit for VECTOR FP LOAD LENGTHENED,
Cornelia Huck <=
- [PULL 17/37] s390x/tcg: Implement 32/128 bit for VECTOR FP COMPARE (AND SIGNAL) SCALAR, Cornelia Huck, 2021/06/21
- [PULL 19/37] s390x/tcg: Implement 128 bit for VECTOR FP LOAD ROUNDED, Cornelia Huck, 2021/06/21
- [PULL 21/37] s390x/tcg: Implement 32/128 bit for VECTOR FP TEST DATA CLASS IMMEDIATE, Cornelia Huck, 2021/06/21
- [PULL 20/37] s390x/tcg: Implement 32/128 bit for VECTOR FP PERFORM SIGN OPERATION, Cornelia Huck, 2021/06/21
- [PULL 23/37] s390x/tcg: Implement VECTOR FP NEGATIVE MULTIPLY AND (ADD|SUBTRACT), Cornelia Huck, 2021/06/21
- [PULL 24/37] s390x/tcg: Implement VECTOR FP (MAXIMUM|MINIMUM), Cornelia Huck, 2021/06/21
- [PULL 22/37] s390x/tcg: Implement 32/128 bit for VECTOR FP MULTIPLY AND (ADD|SUBTRACT), Cornelia Huck, 2021/06/21
- [PULL 25/37] linux-user: elf: s390x: Prepare for Vector enhancements facility, Cornelia Huck, 2021/06/21
- [PULL 27/37] s390x/cpumodel: Bump up QEMU model to a stripped-down IBM z14 GA2, Cornelia Huck, 2021/06/21
- [PULL 26/37] s390x/tcg: We support Vector enhancements facility, Cornelia Huck, 2021/06/21