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[PULL 09/57] target/arm: Factor FP context update code out into helper f
From: |
Peter Maydell |
Subject: |
[PULL 09/57] target/arm: Factor FP context update code out into helper function |
Date: |
Mon, 21 Jun 2021 17:27:45 +0100 |
Factor the code in full_vfp_access_check() which updates the
ownership of the FP context and creates a new FP context
out into its own function.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210618141019.10671-6-peter.maydell@linaro.org
---
target/arm/translate-vfp.c | 104 +++++++++++++++++++++----------------
1 file changed, 58 insertions(+), 46 deletions(-)
diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c
index 8987ef2e5b9..85418dee2e4 100644
--- a/target/arm/translate-vfp.c
+++ b/target/arm/translate-vfp.c
@@ -131,6 +131,62 @@ void gen_preserve_fp_state(DisasContext *s)
}
}
+/*
+ * Generate code for M-profile FP context handling: update the
+ * ownership of the FP context, and create a new context if
+ * necessary. This corresponds to the parts of the pseudocode
+ * ExecuteFPCheck() after the inital PreserveFPState() call.
+ */
+static void gen_update_fp_context(DisasContext *s)
+{
+ /* Update ownership of FP context: set FPCCR.S to match current state */
+ if (s->v8m_fpccr_s_wrong) {
+ TCGv_i32 tmp;
+
+ tmp = load_cpu_field(v7m.fpccr[M_REG_S]);
+ if (s->v8m_secure) {
+ tcg_gen_ori_i32(tmp, tmp, R_V7M_FPCCR_S_MASK);
+ } else {
+ tcg_gen_andi_i32(tmp, tmp, ~R_V7M_FPCCR_S_MASK);
+ }
+ store_cpu_field(tmp, v7m.fpccr[M_REG_S]);
+ /* Don't need to do this for any further FP insns in this TB */
+ s->v8m_fpccr_s_wrong = false;
+ }
+
+ if (s->v7m_new_fp_ctxt_needed) {
+ /*
+ * Create new FP context by updating CONTROL.FPCA, CONTROL.SFPA,
+ * the FPSCR, and VPR.
+ */
+ TCGv_i32 control, fpscr;
+ uint32_t bits = R_V7M_CONTROL_FPCA_MASK;
+
+ fpscr = load_cpu_field(v7m.fpdscr[s->v8m_secure]);
+ gen_helper_vfp_set_fpscr(cpu_env, fpscr);
+ tcg_temp_free_i32(fpscr);
+ if (dc_isar_feature(aa32_mve, s)) {
+ TCGv_i32 z32 = tcg_const_i32(0);
+ store_cpu_field(z32, v7m.vpr);
+ }
+
+ /*
+ * We don't need to arrange to end the TB, because the only
+ * parts of FPSCR which we cache in the TB flags are the VECLEN
+ * and VECSTRIDE, and those don't exist for M-profile.
+ */
+
+ if (s->v8m_secure) {
+ bits |= R_V7M_CONTROL_SFPA_MASK;
+ }
+ control = load_cpu_field(v7m.control[M_REG_S]);
+ tcg_gen_ori_i32(control, control, bits);
+ store_cpu_field(control, v7m.control[M_REG_S]);
+ /* Don't need to do this for any further FP insns in this TB */
+ s->v7m_new_fp_ctxt_needed = false;
+ }
+}
+
/*
* Check that VFP access is enabled. If it is, do the necessary
* M-profile lazy-FP handling and then return true.
@@ -173,52 +229,8 @@ static bool full_vfp_access_check(DisasContext *s, bool
ignore_vfp_enabled)
/* Trigger lazy-state preservation if necessary */
gen_preserve_fp_state(s);
- /* Update ownership of FP context: set FPCCR.S to match current state
*/
- if (s->v8m_fpccr_s_wrong) {
- TCGv_i32 tmp;
-
- tmp = load_cpu_field(v7m.fpccr[M_REG_S]);
- if (s->v8m_secure) {
- tcg_gen_ori_i32(tmp, tmp, R_V7M_FPCCR_S_MASK);
- } else {
- tcg_gen_andi_i32(tmp, tmp, ~R_V7M_FPCCR_S_MASK);
- }
- store_cpu_field(tmp, v7m.fpccr[M_REG_S]);
- /* Don't need to do this for any further FP insns in this TB */
- s->v8m_fpccr_s_wrong = false;
- }
-
- if (s->v7m_new_fp_ctxt_needed) {
- /*
- * Create new FP context by updating CONTROL.FPCA, CONTROL.SFPA,
- * the FPSCR, and VPR.
- */
- TCGv_i32 control, fpscr;
- uint32_t bits = R_V7M_CONTROL_FPCA_MASK;
-
- fpscr = load_cpu_field(v7m.fpdscr[s->v8m_secure]);
- gen_helper_vfp_set_fpscr(cpu_env, fpscr);
- tcg_temp_free_i32(fpscr);
- if (dc_isar_feature(aa32_mve, s)) {
- TCGv_i32 z32 = tcg_const_i32(0);
- store_cpu_field(z32, v7m.vpr);
- }
-
- /*
- * We don't need to arrange to end the TB, because the only
- * parts of FPSCR which we cache in the TB flags are the VECLEN
- * and VECSTRIDE, and those don't exist for M-profile.
- */
-
- if (s->v8m_secure) {
- bits |= R_V7M_CONTROL_SFPA_MASK;
- }
- control = load_cpu_field(v7m.control[M_REG_S]);
- tcg_gen_ori_i32(control, control, bits);
- store_cpu_field(control, v7m.control[M_REG_S]);
- /* Don't need to do this for any further FP insns in this TB */
- s->v7m_new_fp_ctxt_needed = false;
- }
+ /* Update ownership of FP context and create new FP context if needed
*/
+ gen_update_fp_context(s);
}
return true;
--
2.20.1
- [PULL 00/57] target-arm queue, Peter Maydell, 2021/06/21
- [PULL 01/57] hw/acpi: Provide stub version of acpi_ghes_record_errors(), Peter Maydell, 2021/06/21
- [PULL 04/57] docs/system/arm: Document which architecture extensions we emulate, Peter Maydell, 2021/06/21
- [PULL 05/57] target/arm/translate-vfp.c: Whitespace fixes, Peter Maydell, 2021/06/21
- [PULL 06/57] target/arm: Handle FPU being disabled in FPCXT_NS accesses, Peter Maydell, 2021/06/21
- [PULL 03/57] target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors, Peter Maydell, 2021/06/21
- [PULL 10/57] target/arm: Split vfp_access_check() into A and M versions, Peter Maydell, 2021/06/21
- [PULL 02/57] hw/acpi: Provide function acpi_ghes_present(), Peter Maydell, 2021/06/21
- [PULL 08/57] target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access, Peter Maydell, 2021/06/21
- [PULL 11/57] target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m(), Peter Maydell, 2021/06/21
- [PULL 09/57] target/arm: Factor FP context update code out into helper function,
Peter Maydell <=
- [PULL 15/57] target/arm: Implement MVE VCLS, Peter Maydell, 2021/06/21
- [PULL 16/57] target/arm: Implement MVE VREV16, VREV32, VREV64, Peter Maydell, 2021/06/21
- [PULL 07/57] target/arm: Don't NOCP fault for FPCXT_NS accesses, Peter Maydell, 2021/06/21
- [PULL 17/57] target/arm: Implement MVE VMVN (register), Peter Maydell, 2021/06/21
- [PULL 20/57] tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64, Peter Maydell, 2021/06/21
- [PULL 12/57] target/arm: Implement MVE VLDR/VSTR (non-widening forms), Peter Maydell, 2021/06/21
- [PULL 19/57] target/arm: Implement MVE VNEG, Peter Maydell, 2021/06/21
- [PULL 21/57] target/arm: Implement MVE VDUP, Peter Maydell, 2021/06/21
- [PULL 26/57] target/arm: Implement MVE VMAX, VMIN, Peter Maydell, 2021/06/21
- [PULL 23/57] target/arm: Implement MVE VADD, VSUB, VMUL, Peter Maydell, 2021/06/21