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[PULL 45/57] target/arm: Implement MVE VSHL insn
From: |
Peter Maydell |
Subject: |
[PULL 45/57] target/arm: Implement MVE VSHL insn |
Date: |
Mon, 21 Jun 2021 17:28:21 +0100 |
Implement the MVE VSHL insn (vector form).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-35-peter.maydell@linaro.org
---
target/arm/helper-mve.h | 8 ++++++++
target/arm/mve.decode | 3 +++
target/arm/mve_helper.c | 6 ++++++
target/arm/translate-mve.c | 2 ++
4 files changed, 19 insertions(+)
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index 42be99ad526..56b3e8591ad 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -169,6 +169,14 @@ DEF_HELPER_FLAGS_4(mve_vqsubub, TCG_CALL_NO_WG, void, env,
ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vqsubuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vqsubuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vshlsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vshlsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vshlsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+
+DEF_HELPER_FLAGS_4(mve_vshlub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vshluh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+DEF_HELPER_FLAGS_4(mve_vshluw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
+
DEF_HELPER_FLAGS_4(mve_vqshlsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vqshlsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
DEF_HELPER_FLAGS_4(mve_vqshlsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index e78eab6d659..ebf156b46b5 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -130,6 +130,9 @@ VQADD_U 111 1 1111 0 . .. ... 0 ... 0 0000 . 1 . 1
... 0 @2op
VQSUB_S 111 0 1111 0 . .. ... 0 ... 0 0010 . 1 . 1 ... 0 @2op
VQSUB_U 111 1 1111 0 . .. ... 0 ... 0 0010 . 1 . 1 ... 0 @2op
+VSHL_S 111 0 1111 0 . .. ... 0 ... 0 0100 . 1 . 0 ... 0 @2op_rev
+VSHL_U 111 1 1111 0 . .. ... 0 ... 0 0100 . 1 . 0 ... 0 @2op_rev
+
VQSHL_S 111 0 1111 0 . .. ... 0 ... 0 0100 . 1 . 1 ... 0 @2op_rev
VQSHL_U 111 1 1111 0 . .. ... 0 ... 0 0100 . 1 . 1 ... 0 @2op_rev
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index 8ddd07ac287..fa440b13d31 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -521,6 +521,12 @@ DO_2OP_U(vhaddu, do_vhadd_u)
DO_2OP_S(vhsubs, do_vhsub_s)
DO_2OP_U(vhsubu, do_vhsub_u)
+#define DO_VSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false,
NULL)
+#define DO_VSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false,
NULL)
+
+DO_2OP_S(vshls, DO_VSHLS)
+DO_2OP_U(vshlu, DO_VSHLU)
+
static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bool
*s)
{
if (val > max) {
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index bd4c6150cad..487ac3185c6 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -402,6 +402,8 @@ DO_2OP(VQADD_S, vqadds)
DO_2OP(VQADD_U, vqaddu)
DO_2OP(VQSUB_S, vqsubs)
DO_2OP(VQSUB_U, vqsubu)
+DO_2OP(VSHL_S, vshls)
+DO_2OP(VSHL_U, vshlu)
DO_2OP(VQSHL_S, vqshls)
DO_2OP(VQSHL_U, vqshlu)
DO_2OP(VQRSHL_S, vqrshls)
--
2.20.1
- [PULL 27/57] target/arm: Implement MVE VABD, (continued)
- [PULL 27/57] target/arm: Implement MVE VABD, Peter Maydell, 2021/06/21
- [PULL 28/57] target/arm: Implement MVE VHADD, VHSUB, Peter Maydell, 2021/06/21
- [PULL 29/57] target/arm: Implement MVE VMULL, Peter Maydell, 2021/06/21
- [PULL 32/57] target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH, Peter Maydell, 2021/06/21
- [PULL 33/57] target/arm: Implement MVE VADD (scalar), Peter Maydell, 2021/06/21
- [PULL 31/57] target/arm: Implement MVE VMLSLDAV, Peter Maydell, 2021/06/21
- [PULL 35/57] target/arm: Implement MVE VHADD, VHSUB (scalar), Peter Maydell, 2021/06/21
- [PULL 40/57] target/arm: Implement MVE VQDMULL scalar, Peter Maydell, 2021/06/21
- [PULL 36/57] target/arm: Implement MVE VBRSR, Peter Maydell, 2021/06/21
- [PULL 43/57] target/arm: Implement MVE VQSHL (vector), Peter Maydell, 2021/06/21
- [PULL 45/57] target/arm: Implement MVE VSHL insn,
Peter Maydell <=
- [PULL 46/57] target/arm: Implement MVE VRSHL, Peter Maydell, 2021/06/21
- [PULL 39/57] target/arm: Implement MVE VQDMULH and VQRDMULH (scalar), Peter Maydell, 2021/06/21
- [PULL 41/57] target/arm: Implement MVE VQDMULH, VQRDMULH (vector), Peter Maydell, 2021/06/21
- [PULL 56/57] target/arm: Implement MTE3, Peter Maydell, 2021/06/21
- [PULL 49/57] target/arm: Implement MVE VQDMULL (vector), Peter Maydell, 2021/06/21
- [PULL 57/57] docs/system: arm: Add nRF boards description, Peter Maydell, 2021/06/21
- [PULL 44/57] target/arm: Implement MVE VQRSHL, Peter Maydell, 2021/06/21
- [PULL 48/57] target/arm: Implement MVE VQDMLSDH and VQRDMLSDH, Peter Maydell, 2021/06/21
- [PULL 52/57] target/arm: Implement MVE VCADD, Peter Maydell, 2021/06/21
- [PULL 54/57] target/arm: Implement MVE VADDV, Peter Maydell, 2021/06/21