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[PATCH v2 15/29] tcg/mips: Support bswap flags in tcg_out_bswap32
From: |
Richard Henderson |
Subject: |
[PATCH v2 15/29] tcg/mips: Support bswap flags in tcg_out_bswap32 |
Date: |
Mon, 21 Jun 2021 16:18:35 -0700 |
Merge tcg_out_bswap32 and tcg_out_bswap32s.
Use the flags in the internal uses for loads and stores.
For mips32r2 bswap32 with zero-extension, standardize on
WSBH+ROTR+DEXT. This is the same number of insns as the
previous DSBH+DSHD+DSRL but fits in better with the flags check.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/mips/tcg-target.c.inc | 39 ++++++++++++++++-----------------------
1 file changed, 16 insertions(+), 23 deletions(-)
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 7a5634419c..e3698274eb 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -578,27 +578,20 @@ static void tcg_out_bswap_subr(TCGContext *s, const
tcg_insn_unit *sub)
tcg_debug_assert(ok);
}
-static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg)
+static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int flags)
{
if (use_mips32r2_instructions) {
tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16);
+ if (flags & TCG_BSWAP_OZ) {
+ tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0);
+ }
} else {
- tcg_out_bswap_subr(s, bswap32_addr);
- /* delay slot -- never omit the insn, like tcg_out_mov might. */
- tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
- tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
- }
-}
-
-static void tcg_out_bswap32u(TCGContext *s, TCGReg ret, TCGReg arg)
-{
- if (use_mips32r2_instructions) {
- tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
- tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
- tcg_out_dsrl(s, ret, ret, 32);
- } else {
- tcg_out_bswap_subr(s, bswap32u_addr);
+ if (flags & TCG_BSWAP_OZ) {
+ tcg_out_bswap_subr(s, bswap32u_addr);
+ } else {
+ tcg_out_bswap_subr(s, bswap32_addr);
+ }
/* delay slot -- never omit the insn, like tcg_out_mov might. */
tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
@@ -1380,7 +1373,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg
lo, TCGReg hi,
if (TCG_TARGET_REG_BITS == 64 && is_64) {
if (use_mips32r2_instructions) {
tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
- tcg_out_bswap32u(s, lo, lo);
+ tcg_out_bswap32(s, lo, lo, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
} else {
tcg_out_bswap_subr(s, bswap32u_addr);
/* delay slot */
@@ -1393,7 +1386,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg
lo, TCGReg hi,
case MO_SL | MO_BSWAP:
if (use_mips32r2_instructions) {
tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
- tcg_out_bswap32(s, lo, lo);
+ tcg_out_bswap32(s, lo, lo, 0);
} else {
tcg_out_bswap_subr(s, bswap32_addr);
/* delay slot */
@@ -1519,7 +1512,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg
lo, TCGReg hi,
break;
case MO_32 | MO_BSWAP:
- tcg_out_bswap32(s, TCG_TMP3, lo);
+ tcg_out_bswap32(s, TCG_TMP3, lo, 0);
lo = TCG_TMP3;
/* FALLTHRU */
case MO_32:
@@ -1538,9 +1531,9 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg
lo, TCGReg hi,
tcg_out_opc_imm(s, OPC_SW, TCG_TMP0, base, 0);
tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, 4);
} else {
- tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi);
+ tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi, 0);
tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 0);
- tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo);
+ tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo, 0);
tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4);
}
break;
@@ -1945,10 +1938,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
tcg_out_bswap16(s, a0, a1, a2);
break;
case INDEX_op_bswap32_i32:
- tcg_out_bswap32(s, a0, a1);
+ tcg_out_bswap32(s, a0, a1, 0);
break;
case INDEX_op_bswap32_i64:
- tcg_out_bswap32u(s, a0, a1);
+ tcg_out_bswap32(s, a0, a1, a2);
break;
case INDEX_op_bswap64_i64:
tcg_out_bswap64(s, a0, a1);
--
2.25.1
- [PATCH v2 08/29] tcg/ppc: Split out tcg_out_bswap16, (continued)
- [PATCH v2 08/29] tcg/ppc: Split out tcg_out_bswap16, Richard Henderson, 2021/06/21
- [PATCH v2 12/29] tcg/ppc: Use power10 byte-reverse instructions, Richard Henderson, 2021/06/21
- [PATCH v2 07/29] tcg/ppc: Split out tcg_out_sari{32,64}, Richard Henderson, 2021/06/21
- [PATCH v2 05/29] tcg/arm: Support bswap flags, Richard Henderson, 2021/06/21
- [PATCH v2 10/29] tcg/ppc: Split out tcg_out_bswap64, Richard Henderson, 2021/06/21
- [PATCH v2 09/29] tcg/ppc: Split out tcg_out_bswap32, Richard Henderson, 2021/06/21
- [PATCH v2 11/29] tcg/ppc: Support bswap flags, Richard Henderson, 2021/06/21
- [PATCH v2 14/29] tcg/mips: Support bswap flags in tcg_out_bswap16, Richard Henderson, 2021/06/21
- [PATCH v2 16/29] tcg/tci: Support bswap flags, Richard Henderson, 2021/06/21
- [PATCH v2 15/29] tcg/mips: Support bswap flags in tcg_out_bswap32,
Richard Henderson <=
- [PATCH v2 13/29] tcg/s390: Support bswap flags, Richard Henderson, 2021/06/21
- [PATCH v2 17/29] tcg: Handle new bswap flags during optimize, Richard Henderson, 2021/06/21
- [PATCH v2 22/29] target/arm: Improve vector REV, Richard Henderson, 2021/06/21
- [PATCH v2 24/29] target/i386: Improve bswap translation, Richard Henderson, 2021/06/21
- [PATCH v2 19/29] tcg: Make use of bswap flags in tcg_gen_qemu_ld_*, Richard Henderson, 2021/06/21
- [PATCH v2 20/29] tcg: Make use of bswap flags in tcg_gen_qemu_st_*, Richard Henderson, 2021/06/21
- [PATCH v2 18/29] tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64, Richard Henderson, 2021/06/21
- [PATCH v2 25/29] target/sh4: Improve swap.b translation, Richard Henderson, 2021/06/21