RE: [PATCH v5 03/14] target/hexagon: import README for idef-parser

[Taylor Simpson]

> -----Original Message-----
> From: Alessandro Di Federico <ale.qemu@rev.ng>
> Sent: Saturday, June 19, 2021 3:37 AM
> To: qemu-devel@nongnu.org
> Cc: Taylor Simpson <tsimpson@quicinc.com>; Brian Cain
> <bcain@quicinc.com>; babush@rev.ng; nizzo@rev.ng; philmd@redhat.com;
> richard.henderson@linaro.org; Alessandro Di Federico <ale@rev.ng>
> Subject: [PATCH v5 03/14] target/hexagon: import README for idef-parser
> 
> From: Alessandro Di Federico <ale@rev.ng>
> 
> Signed-off-by: Alessandro Di Federico <ale@rev.ng>
> ---
>  target/hexagon/README                 |   5 +
>  target/hexagon/idef-parser/README.rst | 447
> ++++++++++++++++++++++++++
>  2 files changed, 452 insertions(+)
>  create mode 100644 target/hexagon/idef-parser/README.rst
> 
> diff --git a/target/hexagon/README b/target/hexagon/README index
> b0b2435070..2f2814380c 100644
> --- a/target/hexagon/README
> +++ b/target/hexagon/README
> @@ -43,6 +47,7 @@ header files in <BUILD_DIR>/target/hexagon
>          gen_tcg_funcs.py                -> tcg_funcs_generated.c.inc
>          gen_tcg_func_table.py           -> tcg_func_table_generated.c.inc
>          gen_helper_funcs.py             -> helper_funcs_generated.c.inc
> +        gen_idef_parser_funcs.py        -> idef_parser_input.h

The output file is actually named idef_parser_input.h.inc


> a/target/hexagon/idef-parser/README.rst b/target/hexagon/idef-
> parser/README.rst
> new file mode 100644
> index 0000000000..f4cb416e8b
> --- /dev/null
> +++ b/target/hexagon/idef-parser/README.rst
> @@ -0,0 +1,447 @@
> +Hexagon ISA instruction definitions to tinycode generator compiler
> +------------------------------------------------------------------
> +
> +idef-parser is a small compiler able to translate the Hexagon ISA
> +description language into tinycode generator code, that can be easily
> integrated into QEMU.
> +
> +Compilation Example
> +-------------------
> +
> +To better understand the scope of the idef-parser, we'll explore an
> +applicative example. Let's start by one of the simplest Hexagon instruction:
> the ``add``.
> +
> +The ISA description language represents the ``add`` instruction as
> +follows:
> +
> +.. code:: c
> +
> +   A2_add(RdV, in RsV, in RtV) {
> +       { RdV=RsV+RtV;}
> +   }
> +
> +idef-parser will compile the above code into the following code:
> +
> +.. code:: c
> +
> +   /* A2_add */
> +   void emit_A2_add(DisasContext *ctx, Insn *insn, Packet *pkt, TCGv_i32
> RdV,
> +                    TCGv_i32 RsV, TCGv_i32 RtV)
> +   /*  { RdV=RsV+RtV;} */
> +   {
> +       tcg_gen_movi_i32(RdV, 0);
> +       TCGv_i32 tmp_0 = tcg_temp_new_i32();
> +       tcg_gen_add_i32(tmp_0, RsV, RtV);
> +       tcg_gen_mov_i32(RdV, tmp_0);
> +       tcg_temp_free_i32(tmp_0);
> +   }

The output isn't actually indented, but it would be great if it were.  This is 
especially true for instructions where an "if" or "for" show up in the emitted 
code.

> +
> +Another approach to fix QEMU system test, where many instructions might
> +fail, is to compare the execution trace of your implementation with the
> +reference implementations already present in QEMU. To do so you should
> +obtain a QEMU build where the instruction pass the test, and run it with the
> following command:
> +
> +::
> +
> +   sudo unshare -p sudo -u <USER> bash -c \
> +   'env -i <qemu-hexagon full path> -d cpu <TEST>'
> +
> +And do the same for your implementation, the generated execution traces
> +will be inherently aligned and can be inspected for behavioral
> +differences using the ``diff`` tool.

Is there a way to force the parser not to emit a particular instruction (i.e., 
fall back on the reference implementation)?