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[PULL 2/7] target/riscv: gdbstub: Fix dynamic CSR XML generation
From: |
Alistair Francis |
Subject: |
[PULL 2/7] target/riscv: gdbstub: Fix dynamic CSR XML generation |
Date: |
Thu, 24 Jun 2021 05:02:06 -0700 |
From: Bin Meng <bin.meng@windriver.com>
Since commit 605def6eeee5 ("target/riscv: Use the RISCVException enum for CSR
operations")
the CSR predicate() function was changed to return RISCV_EXCP_NONE
instead of 0 for a valid CSR, but it forgot to update the dynamic
CSR XML generation codes in gdbstub.
Fixes: 605def6eeee5 ("target/riscv: Use the RISCVException enum for CSR
operations")
Reported-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210615085133.389887-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/gdbstub.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index ca78682cf4..a7a9c0b1fe 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -170,7 +170,7 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int
base_reg)
for (i = 0; i < CSR_TABLE_SIZE; i++) {
predicate = csr_ops[i].predicate;
- if (predicate && !predicate(env, i)) {
+ if (predicate && (predicate(env, i) == RISCV_EXCP_NONE)) {
if (csr_ops[i].name) {
g_string_append_printf(s, "<reg name=\"%s\"", csr_ops[i].name);
} else {
--
2.31.1
- [PULL 0/7] riscv-to-apply queue, Alistair Francis, 2021/06/24
- [PULL 7/7] hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer, Alistair Francis, 2021/06/24
- [PULL 1/7] target/riscv: Use target_ulong for the DisasContext misa, Alistair Francis, 2021/06/24
- [PULL 2/7] target/riscv: gdbstub: Fix dynamic CSR XML generation,
Alistair Francis <=
- [PULL 3/7] hw/char: Consistent function names for sifive_uart, Alistair Francis, 2021/06/24
- [PULL 4/7] hw/char: QOMify sifive_uart, Alistair Francis, 2021/06/24
- [PULL 5/7] hw/char/ibex_uart: Make the register layout private, Alistair Francis, 2021/06/24
- [PULL 6/7] hw/timer: Initial commit of Ibex Timer, Alistair Francis, 2021/06/24
- Re: [PULL 0/7] riscv-to-apply queue, Peter Maydell, 2021/06/25