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Re: [PULL v2 00/57] target-arm queue


From: Peter Maydell
Subject: Re: [PULL v2 00/57] target-arm queue
Date: Thu, 24 Jun 2021 19:45:30 +0100

On Thu, 24 Jun 2021 at 15:00, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> Squashed in a trivial fix for 32-bit hosts:
>
> --- a/target/arm/mve_helper.c
> +++ b/target/arm/mve_helper.c
> @@ -1120,7 +1120,7 @@ DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
>                      acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
>                                               m[H##ESIZE(e)]));          \
>                  }                                                       \
> -                acc = int128_add(acc, 1 << 7);                          \
> +                acc = int128_add(acc, int128_make64(1 << 7));           \
>              }                                                           \
>          }                                                               \
>          mve_advance_vpt(env);                                           \
>
> -- PMM
>
> The following changes since commit 53f306f316549d20c76886903181413d20842423:
>
>   Merge remote-tracking branch 
> 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-06-21 
> 11:26:04 +0100)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20210624
>
> for you to fetch changes up to 90a76c6316cfe6416fc33814a838fb3928f746ee:
>
>   docs/system: arm: Add nRF boards description (2021-06-24 14:58:48 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * Don't require 'virt' board to be compiled in for ACPI GHES code
>  * docs: Document which architecture extensions we emulate
>  * Fix bugs in M-profile FPCXT_NS accesses
>  * First slice of MVE patches
>  * Implement MTE3
>  * docs/system: arm: Add nRF boards description
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/6.1
for any user-visible changes.

-- PMM



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