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[PATCH v3 14/29] tcg/mips: Support bswap flags in tcg_out_bswap16
From: |
Richard Henderson |
Subject: |
[PATCH v3 14/29] tcg/mips: Support bswap flags in tcg_out_bswap16 |
Date: |
Fri, 25 Jun 2021 23:36:16 -0700 |
Merge tcg_out_bswap16 and tcg_out_bswap16s. Use the flags
in the internal uses for loads and stores.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/mips/tcg-target.c.inc | 63 +++++++++++++++++++--------------------
1 file changed, 30 insertions(+), 33 deletions(-)
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 5944448b2a..a9f9f527f6 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -540,39 +540,37 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
}
}
-static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg)
+static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags)
{
+ /* ret and arg can't be register tmp0 */
+ tcg_debug_assert(ret != TCG_TMP0);
+ tcg_debug_assert(arg != TCG_TMP0);
+
+ /* With arg = abcd: */
if (use_mips32r2_instructions) {
- tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
- } else {
- /* ret and arg can't be register at */
- if (ret == TCG_TMP0 || arg == TCG_TMP0) {
- tcg_abort();
+ tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */
+ if (flags & TCG_BSWAP_OS) {
+ tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */
+ } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
+ tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */
}
-
- tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8);
- tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8);
- tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00);
- tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0);
+ return;
}
-}
-static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg)
-{
- if (use_mips32r2_instructions) {
- tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
- tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret);
+ tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */
+ if (!(flags & TCG_BSWAP_IZ)) {
+ tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */
+ }
+ if (flags & TCG_BSWAP_OS) {
+ tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */
+ tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */
} else {
- /* ret and arg can't be register at */
- if (ret == TCG_TMP0 || arg == TCG_TMP0) {
- tcg_abort();
+ tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */
+ if (flags & TCG_BSWAP_OZ) {
+ tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */
}
-
- tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8);
- tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24);
- tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16);
- tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0);
}
+ tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */
}
static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub)
@@ -1367,14 +1365,14 @@ static void tcg_out_qemu_ld_direct(TCGContext *s,
TCGReg lo, TCGReg hi,
break;
case MO_UW | MO_BSWAP:
tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
- tcg_out_bswap16(s, lo, TCG_TMP1);
+ tcg_out_bswap16(s, lo, TCG_TMP1, TCG_BSWAP_IZ | TCG_BSWAP_OZ);
break;
case MO_UW:
tcg_out_opc_imm(s, OPC_LHU, lo, base, 0);
break;
case MO_SW | MO_BSWAP:
tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0);
- tcg_out_bswap16s(s, lo, TCG_TMP1);
+ tcg_out_bswap16(s, lo, TCG_TMP1, TCG_BSWAP_IZ | TCG_BSWAP_OS);
break;
case MO_SW:
tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
@@ -1514,8 +1512,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg
lo, TCGReg hi,
break;
case MO_16 | MO_BSWAP:
- tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, lo, 0xffff);
- tcg_out_bswap16(s, TCG_TMP1, TCG_TMP1);
+ tcg_out_bswap16(s, TCG_TMP1, lo, 0);
lo = TCG_TMP1;
/* FALLTHRU */
case MO_16:
@@ -1933,10 +1930,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
case INDEX_op_not_i64:
i1 = OPC_NOR;
goto do_unary;
- case INDEX_op_bswap16_i32:
- case INDEX_op_bswap16_i64:
- i1 = OPC_WSBH;
- goto do_unary;
case INDEX_op_ext8s_i32:
case INDEX_op_ext8s_i64:
i1 = OPC_SEB;
@@ -1948,6 +1941,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1);
break;
+ case INDEX_op_bswap16_i32:
+ case INDEX_op_bswap16_i64:
+ tcg_out_bswap16(s, a0, a1, a2);
+ break;
case INDEX_op_bswap32_i32:
tcg_out_bswap32(s, a0, a1);
break;
--
2.25.1
- Re: [PATCH v3 04/29] tcg/aarch64: Support bswap flags, (continued)
- [PATCH v3 10/29] tcg/ppc: Split out tcg_out_bswap64, Richard Henderson, 2021/06/26
- [PATCH v3 12/29] tcg/ppc: Use power10 byte-reverse instructions, Richard Henderson, 2021/06/26
- [PATCH v3 16/29] tcg/tci: Support bswap flags, Richard Henderson, 2021/06/26
- [PATCH v3 15/29] tcg/mips: Support bswap flags in tcg_out_bswap32, Richard Henderson, 2021/06/26
- [PATCH v3 20/29] tcg: Make use of bswap flags in tcg_gen_qemu_st_*, Richard Henderson, 2021/06/26
- [PATCH v3 25/29] target/sh4: Improve swap.b translation, Richard Henderson, 2021/06/26
- [PATCH v3 22/29] target/arm: Improve vector REV, Richard Henderson, 2021/06/26
- [PATCH v3 14/29] tcg/mips: Support bswap flags in tcg_out_bswap16,
Richard Henderson <=
- [PATCH v3 17/29] tcg: Handle new bswap flags during optimize, Richard Henderson, 2021/06/26
- [PATCH v3 24/29] target/i386: Improve bswap translation, Richard Henderson, 2021/06/26
- [PATCH v3 19/29] tcg: Make use of bswap flags in tcg_gen_qemu_ld_*, Richard Henderson, 2021/06/26
- [PATCH v3 13/29] tcg/s390: Support bswap flags, Richard Henderson, 2021/06/26
- [PATCH v3 23/29] target/arm: Improve REVSH, Richard Henderson, 2021/06/26
- [PATCH v3 29/29] tcg/riscv: Remove MO_BSWAP handling, Richard Henderson, 2021/06/26
- [PATCH v3 18/29] tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64, Richard Henderson, 2021/06/26