Re: [PATCH 07/20] target/loongarch: Add fixed point arithmetic instruction translation

[Song Gao]

Hi, Richard,

On 07/02/2021 10:46 PM, Richard Henderson wrote:
> On 7/2/21 1:51 AM, Philippe Mathieu-Daudé wrote:
>> static bool trans_mul_d(DisasContext *ctx, int rd, int rj, int rk)
>> {
>>      TCGv t0, t1;
>>
>>      check_loongarch_64(ctx);
>>
>>      if (a->rd == 0) {
>>          /* Treat as NOP. */
>>          return true;
>>      }
>>
>>      t0 = tcg_temp_new();
>>      t1 = tcg_temp_new();
>>
>>      gen_load_gpr(t0, a->rj);
>>      gen_load_gpr(t1, a->rk);
> 
> Another improvement over mips is possible, while we're at it:
> 
> TCGv get_gpr(int regno)
> {
>     if (regno == 0) {
>         return tcg_constant_tl(0);
>     } else {
>         return cpu_gpr[regno];
>     }
> }
> 
>     t0 = get_gpr(a->rj);
>     t1 = get_gpr(a->rk);
> 
>>
>>      tcg_gen_mul_i64(cpu_gpr[a->rd], t0, t1);
>>
>>      tcg_temp_free(t0);
>>      tcg_temp_free(t1);
> 
> and now the frees are not necessary.
> 
> You do have to be careful that you consume the input before you write back to 
> cpu_gpr[a->rd].  Previously you had a copy, but now t0 and t1 reference the 
> live register.  And of course you cannot write to either t0 or t1, because 
> one of them might be the constant 0.


Got it, thanks for kindly help!

Regards
Song Gao