The offset of XSAVE state components within the XSAVE state area is
currently hard-coded via reference to the X86XSaveArea structure. This
structure is accurate for Intel systems at the time of writing, but
incorrect for newer AMD systems, as the state component for protection
keys is located differently (offset 0x980 rather than offset 0xa80).
For KVM and HVF, replace the hard-coding of the state component
offsets with data derived from CPUID leaf 0xd information.
TCG still uses the X86XSaveArea structure, as there is no underlying
CPU to use in determining appropriate values.
This is a replacement for the changes in
https://lore.kernel.org/r/20210520145647.3483809-1-david.edmondson@oracle.com,
which simply modifed the hard-coded offsets for AMD systems.
Testing on HVF is minimal (it builds and, by observation, the XSAVE
state component offsets reported to a running VM are accurate on an
older Intel system).
David Edmondson (8):
target/i386: Declare constants for XSAVE offsets
target/i386: Consolidate the X86XSaveArea offset checks
target/i386: Clarify the padding requirements of X86XSaveArea
target/i386: Pass buffer and length to XSAVE helper
target/i386: Make x86_ext_save_areas visible outside cpu.c
target/i386: Observe XSAVE state area offsets
target/i386: Populate x86_ext_save_areas offsets using cpuid where
possible
target/i386: Move X86XSaveArea into TCG
target/i386/cpu.c | 18 +--
target/i386/cpu.h | 41 ++----
target/i386/hvf/hvf-cpu.c | 34 +++++
target/i386/hvf/hvf.c | 3 +-
target/i386/hvf/x86hvf.c | 19 ++-
target/i386/kvm/kvm-cpu.c | 36 +++++
target/i386/kvm/kvm.c | 52 +------
target/i386/tcg/fpu_helper.c | 1 +
target/i386/tcg/tcg-cpu.c | 20 +++
target/i386/tcg/tcg-cpu.h | 57 ++++++++
target/i386/xsave_helper.c | 267 ++++++++++++++++++++++++++---------
11 files changed, 381 insertions(+), 167 deletions(-)