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Re: [PATCH v8 3/3] target/i386: Correct implementation for FCS, FIP, FD
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From: |
Ziqiao Kong |
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Subject: |
Re: [PATCH v8 3/3] target/i386: Correct implementation for FCS, FIP, FDS and FDP |
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Date: |
Thu, 8 Jul 2021 10:24:07 +0800 |
Hello!
Thanks for applying fixes for me. Is there anything else I should do?
Ziqiao
On Thu, Jul 8, 2021 at 6:24 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> From: Ziqiao Kong <ziqiaokong@gmail.com>
>
> Update FCS:FIP and FDS:FDP according to the Intel Manual Vol.1 8.1.8.
> Note that CPUID.(EAX=07H,ECX=0H):EBX[bit 13] is not implemented by
> design in this patch and will be added along with TCG features flag
> in a separate patch later.
>
> Signed-off-by: Ziqiao Kong <ziqiaokong@gmail.com>
> Message-Id: <20210530150112.74411-2-ziqiaokong@gmail.com>
> [rth: Push FDS/FDP handling down into mod != 3 case; free last_addr.]
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/i386/cpu.h | 2 ++
> target/i386/tcg/fpu_helper.c | 20 ++++++++++-------
> target/i386/tcg/translate.c | 43 +++++++++++++++++++++++++++++++++++-
> 3 files changed, 56 insertions(+), 9 deletions(-)
>
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 0f7ddbfeae..8921bf5318 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -1435,6 +1435,8 @@ typedef struct CPUX86State {
> FPReg fpregs[8];
> /* KVM-only so far */
> uint16_t fpop;
> + uint16_t fpcs;
> + uint16_t fpds;
> uint64_t fpip;
> uint64_t fpdp;
>
> diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
> index beb63be432..cdd8e9f947 100644
> --- a/target/i386/tcg/fpu_helper.c
> +++ b/target/i386/tcg/fpu_helper.c
> @@ -731,6 +731,10 @@ static void do_fninit(CPUX86State *env)
> {
> env->fpus = 0;
> env->fpstt = 0;
> + env->fpcs = 0;
> + env->fpds = 0;
> + env->fpip = 0;
> + env->fpdp = 0;
> cpu_set_fpuc(env, 0x37f);
> env->fptags[0] = 1;
> env->fptags[1] = 1;
> @@ -2378,19 +2382,19 @@ static void do_fstenv(CPUX86State *env, target_ulong
> ptr, int data32,
> cpu_stl_data_ra(env, ptr, env->fpuc, retaddr);
> cpu_stl_data_ra(env, ptr + 4, fpus, retaddr);
> cpu_stl_data_ra(env, ptr + 8, fptag, retaddr);
> - cpu_stl_data_ra(env, ptr + 12, 0, retaddr); /* fpip */
> - cpu_stl_data_ra(env, ptr + 16, 0, retaddr); /* fpcs */
> - cpu_stl_data_ra(env, ptr + 20, 0, retaddr); /* fpoo */
> - cpu_stl_data_ra(env, ptr + 24, 0, retaddr); /* fpos */
> + cpu_stl_data_ra(env, ptr + 12, env->fpip, retaddr); /* fpip */
> + cpu_stl_data_ra(env, ptr + 16, env->fpcs, retaddr); /* fpcs */
> + cpu_stl_data_ra(env, ptr + 20, env->fpdp, retaddr); /* fpoo */
> + cpu_stl_data_ra(env, ptr + 24, env->fpds, retaddr); /* fpos */
> } else {
> /* 16 bit */
> cpu_stw_data_ra(env, ptr, env->fpuc, retaddr);
> cpu_stw_data_ra(env, ptr + 2, fpus, retaddr);
> cpu_stw_data_ra(env, ptr + 4, fptag, retaddr);
> - cpu_stw_data_ra(env, ptr + 6, 0, retaddr);
> - cpu_stw_data_ra(env, ptr + 8, 0, retaddr);
> - cpu_stw_data_ra(env, ptr + 10, 0, retaddr);
> - cpu_stw_data_ra(env, ptr + 12, 0, retaddr);
> + cpu_stw_data_ra(env, ptr + 6, env->fpip, retaddr);
> + cpu_stw_data_ra(env, ptr + 8, env->fpcs, retaddr);
> + cpu_stw_data_ra(env, ptr + 10, env->fpdp, retaddr);
> + cpu_stw_data_ra(env, ptr + 12, env->fpds, retaddr);
> }
> }
>
> diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
> index 886d3d80f3..888ead0d49 100644
> --- a/target/i386/tcg/translate.c
> +++ b/target/i386/tcg/translate.c
> @@ -5930,6 +5930,8 @@ static target_ulong disas_insn(DisasContext *s,
> CPUState *cpu)
> /* floats */
> case 0xd8 ... 0xdf:
> {
> + bool update_fip = true;
> +
> if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
> /* if CR0.EM or CR0.TS are set, generate an FPU exception */
> /* XXX: what to do if illegal op ? */
> @@ -5942,7 +5944,14 @@ static target_ulong disas_insn(DisasContext *s,
> CPUState *cpu)
> op = ((b & 7) << 3) | ((modrm >> 3) & 7);
> if (mod != 3) {
> /* memory op */
> - gen_lea_modrm(env, s, modrm);
> + AddressParts a = gen_lea_modrm_0(env, s, modrm);
> + TCGv ea = gen_lea_modrm_1(s, a);
> + TCGv last_addr = tcg_temp_new();
> + bool update_fdp = true;
> +
> + tcg_gen_mov_tl(last_addr, ea);
> + gen_lea_v_seg(s, s->aflag, ea, a.def_seg, s->override);
> +
> switch (op) {
> case 0x00 ... 0x07: /* fxxxs */
> case 0x10 ... 0x17: /* fixxxl */
> @@ -6070,20 +6079,24 @@ static target_ulong disas_insn(DisasContext *s,
> CPUState *cpu)
> case 0x0c: /* fldenv mem */
> gen_helper_fldenv(cpu_env, s->A0,
> tcg_const_i32(dflag - 1));
> + update_fip = update_fdp = false;
> break;
> case 0x0d: /* fldcw mem */
> tcg_gen_qemu_ld_i32(s->tmp2_i32, s->A0,
> s->mem_index, MO_LEUW);
> gen_helper_fldcw(cpu_env, s->tmp2_i32);
> + update_fip = update_fdp = false;
> break;
> case 0x0e: /* fnstenv mem */
> gen_helper_fstenv(cpu_env, s->A0,
> tcg_const_i32(dflag - 1));
> + update_fip = update_fdp = false;
> break;
> case 0x0f: /* fnstcw mem */
> gen_helper_fnstcw(s->tmp2_i32, cpu_env);
> tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0,
> s->mem_index, MO_LEUW);
> + update_fip = update_fdp = false;
> break;
> case 0x1d: /* fldt mem */
> gen_helper_fldt_ST0(cpu_env, s->A0);
> @@ -6095,15 +6108,18 @@ static target_ulong disas_insn(DisasContext *s,
> CPUState *cpu)
> case 0x2c: /* frstor mem */
> gen_helper_frstor(cpu_env, s->A0,
> tcg_const_i32(dflag - 1));
> + update_fip = update_fdp = false;
> break;
> case 0x2e: /* fnsave mem */
> gen_helper_fsave(cpu_env, s->A0,
> tcg_const_i32(dflag - 1));
> + update_fip = update_fdp = false;
> break;
> case 0x2f: /* fnstsw mem */
> gen_helper_fnstsw(s->tmp2_i32, cpu_env);
> tcg_gen_qemu_st_i32(s->tmp2_i32, s->A0,
> s->mem_index, MO_LEUW);
> + update_fip = update_fdp = false;
> break;
> case 0x3c: /* fbld */
> gen_helper_fbld_ST0(cpu_env, s->A0);
> @@ -6126,6 +6142,19 @@ static target_ulong disas_insn(DisasContext *s,
> CPUState *cpu)
> default:
> goto unknown_op;
> }
> +
> + if (update_fdp) {
> + int last_seg = s->override >= 0 ? s->override :
> a.def_seg;
> +
> + tcg_gen_ld_i32(s->tmp2_i32, cpu_env,
> + offsetof(CPUX86State,
> + segs[last_seg].selector));
> + tcg_gen_st16_i32(s->tmp2_i32, cpu_env,
> + offsetof(CPUX86State, fpds));
> + tcg_gen_st_tl(last_addr, cpu_env,
> + offsetof(CPUX86State, fpdp));
> + }
> + tcg_temp_free(last_addr);
> } else {
> /* register float ops */
> opreg = rm;
> @@ -6146,6 +6175,7 @@ static target_ulong disas_insn(DisasContext *s,
> CPUState *cpu)
> case 0: /* fnop */
> /* check exceptions (FreeBSD FPU probe) */
> gen_helper_fwait(cpu_env);
> + update_fip = false;
> break;
> default:
> goto unknown_op;
> @@ -6315,9 +6345,11 @@ static target_ulong disas_insn(DisasContext *s,
> CPUState *cpu)
> break;
> case 2: /* fclex */
> gen_helper_fclex(cpu_env);
> + update_fip = false;
> break;
> case 3: /* fninit */
> gen_helper_fninit(cpu_env);
> + update_fip = false;
> break;
> case 4: /* fsetpm (287 only, just do nop here) */
> break;
> @@ -6438,6 +6470,15 @@ static target_ulong disas_insn(DisasContext *s,
> CPUState *cpu)
> goto unknown_op;
> }
> }
> +
> + if (update_fip) {
> + tcg_gen_ld_i32(s->tmp2_i32, cpu_env,
> + offsetof(CPUX86State, segs[R_CS].selector));
> + tcg_gen_st16_i32(s->tmp2_i32, cpu_env,
> + offsetof(CPUX86State, fpcs));
> + tcg_gen_st_tl(tcg_constant_tl(pc_start - s->cs_base),
> + cpu_env, offsetof(CPUX86State, fpip));
> + }
> }
> break;
> /************************/
> --
> 2.25.1
>
- [PATCH v8 0/3] target/i386: Implement FCS:FIP, FDS:FDP, Richard Henderson, 2021/07/07
- [PATCH v8 2/3] target/i386: Split out do_fninit, Richard Henderson, 2021/07/07
- [PATCH v8 3/3] target/i386: Correct implementation for FCS, FIP, FDS and FDP, Richard Henderson, 2021/07/07
- Re: [PATCH v8 3/3] target/i386: Correct implementation for FCS, FIP, FDS and FDP,
Ziqiao Kong <=
- [PATCH v8 1/3] target/i386: Trivial code motion and code style fix, Richard Henderson, 2021/07/07